DP8500 datasheet(65/70 Pages) NSC

65 / 70 page

160 Functional Differences

between the DP8520A21A22A

and the DP85202122

1 Extending the Column Address Strobe (CAS)

CAS can be extended indefinitely after AREQ transitions

high in non-interleaved mode only providing that the user

program the DP8520A21A22A with the ECAS0 (negat-

ed) during programming To extend CAS the user contin-

ues to assert any or multiple ECASs after negating

AREQ Extending CAS with RAS negated can be used to

gain RAS precharge time By negating AREQ RAS will be

negated The user can then continue to assert a one or

both of the ECASs which will keep CAS asserted By

keeping CAS asserted with RAS negated the VRAM will

keep the data valid until CAS is negated Even though

CAS will be extended DTACK output will always end

from AREQ negated

2 Extending DT OE Functionality

The DT OE output will follow the CAS output during a

VRAM read access and will remain negated during a

VRAM write access For the DP85202122 the DT OE

output remained negated for all VRAM access cycles

This will allow the VRAM to drive the data bus There are

2 options for the function of the DT OE output during a

video shift register load operation With ECAS0 negated

during programming the DT OE output will follow the

VSRL input during video shift register load operations

With the ECAS0 asserted during programming VSRL will

assert DT OE VSRL negated before four rising clock

edges will cause DT OE to be negated VSRL asserted

more than four rising clock edges will cause DT OE to be

negated from the fourth rising clock edge

3 Dual Accessing

RAS will be asserted either one or two clock periods after

GRANTB has been asserted The amount of RAS low

and high time programmed by bits R0 and R1 deter-

mines the number of clock periods after GRANTB chang-

es before RAS will start This is shown in the table below

RAS

RAS Asserted

RAS Asserted from

R0 R1 Precharge

During

GRANTB Change

Time

Refresh

0 0

1 Rising Clock Edge

0 1

1 Rising Clock Edge

1 0

2 Rising Clock Edges

1 1

2 Rising Clock Edges

4 Refresh Clock Counter

The refresh clock counter will count and assert RFRQ

externally when it is time to do a refresh This will occur

even when internal refreshes are disabled This allows

the user to run the chip in a requestacknowledge mode

for refreshing ECAS0 is used to program the RFIP output

to act as either refresh request (RFRQ) or RFIP ECAS0

asserted during programming causes the RFIP output to

function as RFIP ECAS0 negated during programming

causes the RFIP output to function as RFRQ

5 Clearing the Refresh Clock

The refresh clock counter is cleared by negating

DISRFSH and asserting RFSH for at least 500 ns

170 DP8520A21A22A User Hints

1 All inputs to the DP8520A21A22A should be tied high

low or the output of some other device

Note One signal is active high COLINC (EXTNDRF) should be tied low

to disable

2 Each ground on the DP8520A21A22A must be decou-

pled to the closest on-chip supply (VCC) with 01 mF ce-

ramic capacitor

This is necessary because these

grounds are kept separate inside the DP8520A21A

22A The decoupling capacitors should be placed as

close as possible with short leads to the ground and sup-

ply pins of the DP8520A21A22A

3 The output called ‘‘CAP’’ should have a 01 mF capacitor

to ground

4 The DP8520A21A22A has 20X series damping resis-

tors built into the output drivers of RAS CAS address

and DT OE Space should be provided for external

damping resistors on the printed circuit board (or wire-

wrap board) because they may be needed The value of

these damping resistors (if needed) will vary depending

upon the output the capacitance of the load and the

characteristics of the trace as well as the routing of the

trace The value of the damping resistor also may vary

between the wire-wrap board and the printed circuit

board To determine the value of the series damping re-

sistor it is recommended to use an oscilloscope and look

at the furthest VRAM from the DP8520A21A22A The

undershoot of RAS CAS DT OE and the addresses

should be kept to less than 05V below ground by varying

the value of the damping resistor The damping resistors

should be placed as close as possible with short leads to

the driver outputs of the DP8520A21A22A

5 The circuit board must have a good VCC and ground

plane connection If the board is wire-wrapped the VCC

and ground pins of the DP8520A21A22A the VRAM

associated logic and buffer circuitry must be soldered to

the VCC and ground planes

6 The traces from the DP8520A21A22A to the VRAM

should be as short as possible

7 ECAS0 should be held low during programming if the user

wishes that the DP8520A21A22A be compatible with a

DP85202122 design

180 Description of a DP8522A

DP8500 System Interface

Several simple block and timing diagrams are inserted to

help the user design a system interface between the

DP8520A21A22A VRAM controller and the Raster Graph-

ics Processor DP8500 (as shown in

Figure 70 ) For access-

ing the VRAM the DP8520A21A22A uses the RGP’s

PHI 2 clock as an input clock and it runs in Mode 1 (asyn-

chronous mode) This allows the user to guarantee row col-

umn and bank address set up times to a rising clock edge

(as shown in timing calculations provided) This system de-

sign uses a PAL

to interface the access request logic and

the wait logic between the DP8522A and the RGP External

logic is also needed for plane control

DP8500 Datasheet(PDF) 65 Page - National Semiconductor (TI)

DP8500 Datasheet(HTML) 65 Page - National Semiconductor (TI)

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