DP8500 datasheet(34/70 Pages) NSC

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80 RAS and CAS Configuration Modes (Continued)

82 MEMORY INTERLEAVING

Memory interleaving allows the cycle time of VRAMs to be

reduced by having sequential accesses to different memory

banks Since the DP8520A21A22A have separate pre-

charge counters per bank sequential accesses will not be

delayed if the accessed banks use different RAS outputs

To ensure different RAS outputs will be used a mode is

selected where either one or two RAS outputs will be as-

serted during an access The bank select or selects B0 and

B1 are then tied to the least significant address bits caus-

ing a different group of RASs to assert during each sequen-

tial access as shown in

Figure 39 In this figure there should

be at least one clock period of all RAS’s negated between

different RAS’s being asserted to avoid the condition of a

CAS before RAS refresh cycle

83 ADDRESS PIPELINING

Address pipelining allows several access RASstobeas-

serted at once Because RASs can overlap each bank re-

quires either a mode where one RAS and one CAS are used

per bank as shown in

Figure 40 or where two RASs and two

CASs are used per bank as shown in

Figure 41 In order to

perform byte writing while using address pipelining external

gating on the CAS outputs must be used If the array is not

layed out this way a CAS to a bank can be low before RAS

which will cause a refresh of the VRAM not an access To

take full advantage of address pipelining memory interleav-

ing is used To memory interleave the least significant ad-

dress bits should be tied to the bank select inputs to ensure

that all ‘‘back to back’’ sequential accesses are not delayed

since different memory banks are accessed

TLF9338 – 90

FIGURE 39 Memory Interleaving with Byte Writing Capability (C6 C5 C4 e 1 1 0 during Programming)

DP8500 Datasheet(PDF) 34 Page - National Semiconductor (TI)