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CS47L35 Datasheet(PDF) 44 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 44 Page - Cirrus Logic |
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44 / 300 page ![]() 44 DS1085F3 CS47L35 4.3 Digital Core Figure 4-12. Digital-Core Inputs 4.3.3 Digital-Core Output Mixers The digital core comprises multiple output paths. The output paths associated with AIF1–AIF3 are shown in Fig. 4-13. The output paths associated with OUT1, OUT4, and OUT5 are shown in Fig. 4-14. The output paths associated with the SLIMbus interface are shown in Fig. 4-15. A four-input mixer is associated with each output. The four input sources are selectable in each case, and independent volume control is provided for each path. The AIF1–AIF3 output mixer control fields (see Fig. 4-13) are located at register addresses R1792–R1935 (0x0700–0x078F). The OUT1, OUT4, and OUT5 output mixer control fields (see Fig. 4-14) are located at addresses R1664–R1743 (0x0680–0x06CF). The SLIMbus output mixer control fields (see Fig. 4-15) are located at addresses R1984–R2031 (0x07C0–0x07EF). The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are provided in Table 4-7. The x_SRCn fields select the input sources for the respective mixers. Note that the selected input sources must be configured for the same sample rate as the mixer to which they are connected. Sample-rate conversion functions are available to support flexible interconnectivity; see Section 4.3.14. The x_SRCn fields for all digital core functions should be held at 0x00 if SYSCLK is not enabled—SYSCLK must be present and enabled before selecting other values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring SYSCLK while digital core mixers are enabled). The sample rate for the output signal paths is configured using the applicable OUT_RATE, AIFn_RATE, or SLIMTXn_ RATE fields; see Table 4-21. Note that sample-rate conversion is required when routing the output signal paths to any signal chain that is configured for a different sample rate. Silence (mute) (0x00) AEC1 Loopback (0x08) AEC2 Loopback (0x09) IN1L signal path (0x10) IN1R signal path (0x11) IN2L signal path (0x12) IN2R signal path (0x13) AIF1 RX1 (0x20) AIF1 RX2 (0x21) AIF1 RX3 (0x22) AIF1 RX4 (0x23) AIF1 RX5 (0x24) AIF1 RX6 (0x25) AIF2 RX1 (0x28) AIF2 RX2 (0x29) AIF3 RX1 (0x30) AIF3 RX2 (0x31) SLIMbus RX1 (0x38) SLIMbus RX2 (0x39) SLIMbus RX3 (0x3A) SLIMbus RX4 (0x3B) SLIMbus RX5 (0x3C) SLIMbus RX6 (0x3D) |
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