CS47L35 datasheet(83/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.4 DSP Firmware Control

4.4.3

DSP Direct Memory Access (DMA) Control

Each DSP provides a multichannel DMA function; this is configured using the registers described in Table 4-26.

Table 4-25. DSP Memory and Clocking Control

Bit

Label

Default

Description

DSP1 Base Address = R1048064 (0x0F_FE00)

DSP2 Base Address = R1572352 (0x17_FE00)

DSP3 Base Address = R2096640 (0x1F_FE00)

Base address

DSPn_Config_1

18:16 DSPn_CLK_SEL[2:0]

000

DSPn clock frequency select

000 = 5.5 MHz to 9.375 MHz

001 = 9.375 MHz to 18.75 MHz

010 = 18.75 MHz to 37.5 MHz

011 = 37.5 MHz to 75 MHz

100 = 75 MHz to 150 MHz

All other codes are reserved.

Note that, because DSPCLK could be any frequency (within the valid

ranges), it is not possible to quote exact frequencies in this field definition.

The DSPn Clock must be less than or equal to the DSPCLK frequency. The

exact frequency is derived as DSPCLK divided by 1, 2, 4, 8, or 16.

4DSPn_MEM_ENA

DSPn memory control

0 = Disabled

1 = Enabled

The DSPn memory contents are lost when DSPn_MEM_ENA =0. Note that

this bit is not affected by software reset; it remains in its previous condition.

1DSPn_CORE_ENA

DSPn enable. Controls the DSPn firmware execution

0 = Disabled

1 = Enabled

0DSPn_START

—

DSPn start

Write 1 to start DSPn firmware execution

Base address +0x06

DSPn_Status_2

31:16 DSPn_DUALMEM_

COLLISION_

ADDR[15:0]

0x0000 DSPn dual memory collision address. In the event of a DSPn memory access

collision, this field reports the address at which the collision occurred.

The address is defined relative to the base address of the shared data

memory. The LSB represents one 24-bit DSP memory word.

Note: Valid for DSP2 and DSP3 only.

3:1

DSPn_CLK_SEL_

STS[2:0]

000

DSPn clock frequency (read only). Valid only when the respective DSP Core

is enabled.

000 = 5.5 MHz to 9.375 MHz

001 = 9.375 MHz to 18.75 MHz

010 = 18.75 MHz to 37.5 MHz

011 = 37.5 MHz to 75 MHz

100 = 75 MHz to 150 MHz

All other codes are reserved

Note that, because DSPCLK could be any frequency (within the valid

ranges), it is not possible to quote exact frequencies in this field definition.

The exact frequency is derived as DSPCLK divided by 1, 2, 4, 8, or 16.

0DSPn_CLK_AVAIL

DSPn clock availability (read only)

0 = No Clock

1 = Clock Available

This bit exists for legacy software support only; it is not recommended for

future designs—it may be unreliable on the latest device architectures.

Base address +0x38

DSPn_External_Start

4:0

DSPn_START_IN_

SEL[4:0]

0x00

DSPn firmware execution control. Selects the trigger for DSPn firmware

execution.

0x00 = DMA

0x01 = DSP1 Start 1

0x02 = DSP1 Start 2

0x03 = DSP2 Start 1

0x04 = DSP2 Start 2

0x05 = DSP3 Start 1

0x06 = DSP3 Start 2

0x0B = IRQ2

0x10 = Event Logger 1

0x11 = Event Logger 2

0x12 = Event Logger 3

0x13 = Event Logger 4

All other codes are reserved.

Note that the DSPn_START bit also starts the DSPn firmware execution,

regardless of this field setting.

CS47L35 Datasheet(PDF) 83 Page - Cirrus Logic

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