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CS47L35 Datasheet(PDF) 24 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 24 Page - Cirrus Logic |
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24 / 300 page ![]() 24 DS1085F3 CS47L35 3 Characteristics and Specifications Table 3-22. JTAG Interface Timing Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); TCK slew (20%–80%) = 5ns; with the exception of the conditions noted, the following electrical characteristics are valid across the full range of recommended operating conditions. Parameter 1 1.JTAG Interface timing Symbol Minimum Typical Maximum Units TCK cycle time TCCY 50 — — ns TCK pulse width high TCCH 20 — — ns TCK pulse width low TCCL 20 — — ns TMS setup time to TCK rising edge TMSU 1— — ns TMS hold time from TCK rising edge TMH 2— — ns TDI setup time to TCK rising edge TDSU 1— — ns TDI hold time from TCK rising edge TDH 2— — ns TDO propagation delay from TCK falling edge TDD 0— 17 ns TRST setup time to TCK rising edge TRSU 3— — ns TRST hold time from TCK rising edge TRH 3— — ns TRST pulse width low — 20 — — ns TCK (input) tCCH tCCL tCCY TDI (input) tDSU tDH TMS (input) tMSU tMH TDO (output) tDD TRST (input) tRSU tRH |
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