CS47L35 datasheet(10/300 Pages) CIRRUS

10 / 300 page

DS1085F3

CS47L35

3 Characteristics and Specifications

Table 3-1 defines parameters as they are characterized in this section.

Table 3-1. Parameter Definitions

Parameter

Definition

Channel separation

Left-to-right and right-to-left channel separation is the difference in level between the active channel (driven to

maximum full scale output) and the measured signal level in the idle channel at the test signal frequency. The active

channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured

at the output of the associated idle channel.

Common-mode rejection

ratio (CMRR)

The ratio of a specified input signal (applied to both sides of a differential input), relative to the output signal that

results from it.

Dynamic range (DR)

A measure of the difference between the maximum full scale output signal and the sum of all harmonic distortion

products plus noise, with a low-level input signal applied. Typically, an input signal level 60 dB below full scale is

used.

Power-supply rejection

ratio (PSRR)

The ratio of a specified power supply variation relative to the output signal that results from it. PSRR is measured

under quiescent signal path conditions.

Signal-to-noise ratio

(SNR)

A measure of the difference in level between the maximum full scale output signal and the output with no input signal

applied.

Total harmonic distortion

(THD)

The ratio of the RMS sum of the harmonic distortion products in the specified bandwidth 1 relative to the RMS

amplitude of the fundamental (i.e., test frequency) output.

1.All performance measurements are specified with a 20-kHz low-pass brick-wall filter and, where noted, an A-weighted filter. The low-pass filter

removes out-of-band noise.

Total harmonic distortion

plus noise (THD+N)

The ratio of the RMS sum of the harmonic distortion products plus noise in the specified bandwidth 1 relative to the

RMS amplitude of the fundamental (i.e., test frequency) output.

Table 3-2. Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits.

Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified.

Parameter

Symbol

Minimum

Maximum

Supply voltages

DCVDD [1], FLLVDD [1]

CPVDD1, CPVDD2

DBVDD1, DBVDD2, AVDD [2], MICVDD

SPKVDD

1.The DCVDD and FLLVDD pins should be tied together. The associated power domain is referred to as DCVDD.

2.The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD.

–0.3 V

1.6 V

2.5 V

5.0 V

6.0 V

Voltage range digital inputs

DBVDD1 domain

DBVDD2 domain

—

SUBGND – 0.3 V

DBVDD1 + 0.3 V

DBVDD2 + 0.3 V

Voltage range analog inputs

IN1Axx, IN2xx

IN1Bxx

HPOUTFBn 3

MICDETn 3

JACKDET1, HPDETL, HPDETR

JACKDET2 [4], GPSWP, GPSWN

3.The HPOUTFBn and MICDETn functions share common pins. The absolute maximum rating varies according to the applicable function of each pin.

4.If AVDD > MICVDD (e.g., if LDO2 is disabled), the maximum JACKDET2 voltage is AVDD + 0.3 V.

SUBGND – 0.3 V

SUBGND – 0.9 V

SUBGND – 0.3 V

CP1VOUT2N – 0.3 V [5]

SUBGND – 0.3 V

5.CP1VOUT2N is an internal supply, generated by the CS47L35 charge pump (CP1). Its voltage can vary between CPGND and –CPVDD1.

MICVDD + 0.3 V

SUBGND + 0.3 V

MICVDD + 0.3 V

AVDD + 0.3 V

MICVDD + 0.3 V

Ground

AGND 6, DGND, CPGND, SPKGND

6.The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND.

SUBGND – 0.3 V

SUBGND + 0.3 V

Operating temperature range

–40ºC

+85ºC

Operating junction temperature

–40ºC

+125ºC

Storage temperature after soldering

—

–65ºC

+150ºC

ESD-sensitive device. The CS47L35 is manufactured on a CMOS process. It is therefore generically susceptible to damage from

excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. This device is qualified

to current JEDEC ESD standards.

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