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CS47L35 Datasheet(PDF) 92 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 92 Page - Cirrus Logic |
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92 / 300 page  92 DS1085F3 CS47L35 4.5 DSP Peripheral Control R262406 (0x40106) MIF1_CONFIG_4 20:0 MIF1_TX_ LENGTH[20:0] 0x00_ 0000 Selects the total number of data bytes in an I2C Write operation. 0x00_0000 = 1 byte 0x00_0001 = 2 bytes 0x00_0002 = 3 bytes … 0x1F_FFFF = 2,097,152 bytes R262416 (0x40110) MIF1_CONFIG_5 20:0 MIF1_RX_ LENGTH[20:0] 0x00_ 0000 Selects the total number of data bytes in an I2C Read operation. 0x00_0000 = 1 byte 0x00_0001 = 2 bytes 0x00_0002 = 3 bytes … 0x1F_FFFF = 2,097,152 bytes R262418 (0x40112) MIF1_CONFIG_6 7:0 MIF1_TX_BLOCK_ LENGTH[7:0] 0x10 Selects the interval at which the MIF1_BLOCK Interrupt is triggered during I2C Write operations. 0x00 = 1 byte 0x01 = 1 byte 0x02 = 2 bytes … 0x10 = 16 bytes All other codes are reserved R262420 (0x40114) MIF1_CONFIG_7 7:0 MIF1_RX_BLOCK_ LENGTH[7:0] 0x10 Selects the interval at which the MIF1_BLOCK Interrupt is triggered during I2C Read operations. 0x00 = 1 byte 0x01 = 1 byte 0x02 = 2 bytes … 0x10 = 16 bytes All other codes are reserved R262422 (0x40116) MIF1_CONFIG_8 4 MIF1_RX_DONE 0 RX Buffer access control bit. Write 1 to indicate that data in the RX Buffer has been read. In normal operation, a 1 is written after reading the RX buffer. This causes the MIF1_RX_REQUEST bit to be cleared. (Note that, if further data is available to read, the MIF1_RX_REQUEST bit remains set in this case.) 0 MIF1_TX_DONE 0 TX Buffer access control bit. Write 1 to indicate the TX Buffer has been filled with data for transmission. In normal operation, a 1 is written after writing the TX buffer. This causes the MIF1_TX_REQUEST bit to be cleared. R262528 (0x40180) MIF1_STATUS_1 8 MIF1_BUSY_STS 0 MIF Busy Status. This bit, when set, indicates that the master interface is executing an I2C transaction. 8 MIF1_RX_REQUEST 0 RX Buffer flow control bit 0 = No data available to read 1 = Buffer data is available to read 1 MIF1_TX_REQUEST 0 TX Buffer flow control bit 0 = TX buffer not available to write 1 = TX buffer is available to write R262530 (0x40182) MIF1_STATUS_2 20:0 MIF1_BYTE_ COUNT[20:0] 0x00_ 0000 Number of data bytes transferred in current transaction. Note that this field is cleared on completion of the I2C transaction. R262656 (0x40200) MIF1_TX_1 31:24 MIF1_TX_BYTE4[7:0] 0x00 TX Byte 4 23:16 MIF1_TX_BYTE3[7:0] 0x00 TX Byte 3 15:8 MIF1_TX_BYTE2[7:0] 0x00 TX Byte 2 7:0 MIF1_TX_BYTE1[7:0] 0x00 TX Byte 1 R262658 (0x40202) MIF1_TX_2 31:24 MIF1_TX_BYTE8[7:0] 0x00 TX Byte 8 23:16 MIF1_TX_BYTE7[7:0] 0x00 TX Byte 7 15:8 MIF1_TX_BYTE6[7:0] 0x00 TX Byte 6 7:0 MIF1_TX_BYTE5[7:0] 0x00 TX Byte 5 Table 4-30. Master Interface (MIF1) Control (Cont.) Register Address Bit Label Default Description |
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