CS47L35 datasheet(19/300 Pages) CIRRUS

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DS1085F3

CS47L35

3 Characteristics and Specifications

2.Digital speaker (PDM) interface timing—Mode B

Table 3-16. Digital Audio Interface—Master Mode

Test conditions (unless specified otherwise): CLOAD = 25 pF (output pins); BCLK slew (10% to 90%) = 3.7–5.6 ns; with the exception of the conditions

noted, the following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter 1

1.Digital audio interface timing—Master Mode. Note that BCLK and LRCLK outputs

can be inverted if required; the figure shows the default, noninverted polarity.

Symbol

Minimum

Typical

Maximum

Units

Master Mode

AIFnBCLK cycle time

tBCY

—

AIFnBCLK pulse width high

tBCH

—

AIFnBCLK pulse width low

tBCL

—

AIFnLRCLK propagation delay from BCLK falling edge 2

2.The timing of the AIFnLRCLK signal is selectable. If the LRCLK advance option is enabled, the LRCLK transition is timed relative to the preceding

BCLK edge. Under the required condition that BCLK is inverted in this case, the LRCLK transition is still timed relative to the falling BCLK edge.

tLRD

0—

8.3

AIFnTXDAT propagation delay from BCLK falling edge

tDD

0—5

AIFnRXDAT setup time to BCLK rising edge

tDSU

—

AIFnRXDAT hold time from BCLK rising edge

tDH

0—

—

Master Mode,

Slave LRCLK

AIFnLRCLK setup time to BCLK rising edge

tLRSU

—

AIFnLRCLK hold time from BCLK rising edge

tLRH

0—

—

Note: The descriptions above assume noninverted polarity of AIFnBCLK.

(right data)

(left data)

VOL

SPKCLK

(output)

SPKDAT

(output)

tLDIS

tRDIS

tLEN

tCY

tREN

VOL

VOH

BCLK

(output)

LRCLK

(output)

TXDAT

(output)

RXDAT

(input)

tDD

tDH

tDSU

tLRD

tBCH

tBCL

tBCY

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