CS47L35 datasheet(63/300 Pages) CIRRUS

63 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

The S/PDIF output generator should be kept disabled (SPD1_ENA = 0) if SYSCLK is not enabled. The x_SRCn fields for

all digital core functions should be held at 0x00 if SYSCLK is not enabled. SYSCLK must be present and enabled before

selecting other values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring

SYSCLK while digital core functions are enabled).

The sample rate of the S/PDIF generator is configured using SPD1_RATE; see Table 4-21. The S/PDIF transmitter

supports sample rates in the range 32–192 kHz. Note that sample-rate conversion is required when linking the S/PDIF

generator to any signal chain that is configured for a different sample rate.

The SPD1_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn

fields must be cleared before writing a new value to SPD1_RATE. A minimum delay of 125

s must be allowed between

clearing the x_SRCn fields and writing to SPD1_RATE. See Table 4-21 for details.

The S/PDIF generator is enabled by setting SPD1_ENA, as described in Table 4-16.

The S/PDIF output contains audio data derived from the selected sources. Audio samples up to 24-bit width can be

accommodated. The validity bits and the channel status bits in the S/PDIF data are configured using the corresponding

fields in registers R1474 (0x5C2) to R1477 (0x5C5).

Refer to the S/PDIF specification (IEC 60958-3 Digital Audio Interface - Consumer) for full details of the S/PDIF protocol

and configuration parameters.

The CS47L35 automatically checks to confirm whether the SYSCLK frequency is high enough to support the digital mixer

paths. If an attempt is made to enable the S/PDIF generator, and there are insufficient SYSCLK cycles to support it, the

attempt does not succeed. Note that any active signal paths are unaffected under such circumstances.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

4.3.9

Tone Generator

The CS47L35 incorporates a tone generator that can be used for beep functions through any of the audio signal paths.

The tone generator provides two 1-kHz outputs, with configurable phase relationship, offering flexibility to create

differential signals or test scenarios.

Table 4-16. S/PDIF Output Generator Control

Bit

Label

Default

Description

R1474 (0x05C2)

SPD1_TX_Control

SPD1_VAL2

S/PDIF Validity (Subframe B)

SPD1_VAL1

S/PDIF Validity (Subframe A)

SPD1_ENA

S/PDIF Generator Enable

0 = Disabled

1 = Enabled

R1475 (0x05C3)

SPD1_TX_

Channel_Status_1

15:8 SPD1_CATCODE[7:0]

0x00

S/PDIF Category code

7:6 SPD1_CHSTMODE[1:0]

S/PDIF Channel Status mode

5:3 SPD1_PREEMPH[2:0]

000

S/PDIF Preemphasis mode

SPD1_NOCOPY

S/PDIF Copyright status

SPD1_NOAUDIO

S/PDIF Audio/nonaudio indication

SPD1_PRO

S/PDIF Consumer Mode/Professional Mode

R1476 (0x05C4)

SPD1_TX_

Channel_Status_2

15:12 SPD1_FREQ[3:0]

0000

S/PDIF Indicated sample frequency

11:8 SPD1_CHNUM2[3:0]

1011

S/PDIF Channel number (Subframe B)

7:4 SPD1_CHNUM1[3:0]

0000

S/PDIF Channel number (Subframe A)

3:0 SPD1_SRCNUM[3:0]

0001

S/PDIF Source number

R1477 (0x05C5)

SPD1_TX_

Channel_Status_3

11:8 SPD1_ORGSAMP[3:0]

0000

S/PDIF Original sample frequency

7:5 SPD1_TXWL[2:0]

000

S/PDIF Audio sample word length

SPD1_MAXWL

S/PDIF Maximum audio sample word length

3:2 SPD1_SC31_30[1:0]

S/PDIF Channel Status [31:30]

1:0 SPD1_CLKACU[1:0]

Transmitted Clock accuracy

CS47L35 Datasheet(PDF) 63 Page - Cirrus Logic

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