CS47L35 datasheet(33/300 Pages) CIRRUS

33 / 300 page

DS1085F3

CS47L35

4.2 Input Signal Path

Figure 4-9. DMIC Input

Two DMIC channels are interleaved on DMICDATn. The DMIC interface timing is shown in Fig. 4-10. Each microphone

must tristate its data output when the other microphone is transmitting.

Figure 4-10. DMIC Interface Timing

When DMIC input is enabled, the CS47L35 outputs a clock signal on the applicable DMICCLK pins. The DMICCLK

frequency is selectable, as described in Table 4-1.

Note that SYSCLK must be present and enabled when using the DMIC inputs; see Section 4.16 for details regarding

SYSCLK and the associated registers.

4.2.4

Input Signal Path Enable

The input signal paths are enabled using the bits described in Table 4-2. The respective bits must be enabled for analog

or digital input on the respective input paths.

Digital Mic

MICVDD or MICBIASnx

AGND

Digital Mic

VDD

CLK DATA

VDD CLK DATA

CHAN

VDD

DMICDATn

DMICCLKn

Digital

Microphone

Interface

The DMIC inputs are referenced to

MICVDD, MICBIAS1B, MICBIAS2A, or

MICBIAS2B.

The supply for each digital microphone

should provide the same voltage as the

applicable reference.

DMICCLKn pin

DMICDATn pin

(Left and right channels interleaved)

Left mic output

Right mic output

Hi-Z

CS47L35 Datasheet(PDF) 33 Page - Cirrus Logic