CS47L35 datasheet(11/300 Pages) CIRRUS

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DS1085F3

CS47L35

3 Characteristics and Specifications

Table 3-3. Recommended Operating Conditions

Parameter

Symbol

Minimum

Typical

Maximum Units

Digital supply range 1

Digital supply range

1.The DCVDD and FLLVDD pins should be tied together. The associated power domain is referred to as DCVDD.

Core and FLL

I/O

DCVDD [2], FLLVDD [3]

DBVDD1, DBVDD2

2.Sleep mode is supported for when DCVDD is below the limits noted, provided that AVDD and DBVDD1 are present

3.It is recommended to connect a 4.7-

 resistor in series with the FLLVDD pin connection. Note that the minimum voltage limit applies at the supply

end of the 4.7-

 resistor in this case.

1.14

1.71

1.2

—

1.26

3.6 [4]

4.If the SLIMbus interface is enabled, the maximum DBVDD1 voltage is 1.98 V.

Charge pump supply range

CPVDD1

CPVDD2

CPVDD1

CPVDD2

1.71

1.14

1.8

1.2

1.89

1.26

Speaker supply range

SPKVDD

2.4

5.5

Analog supply range 5,6

5.The AVDD1 and AVDD2 pins should be tied together. The associated power domain is referred to as AVDD

6.The AGND1 and AGND2 pins should be tied together. The associated ground domain is referred to as AGND

AVDD

1.71

1.8

1.89

Mic bias supply 7

7.An internal charge pump and LDO (powered by CPVDD1) provide the mic bias supply; the MICVDD pin must not be connected to an external supply.

MICVDD

0.9

2.5

3.78

Ground 8

8.The impedance between DGND, AGND, and SUBGND must not exceed 0.1

.

The impedance between SPKGND and SUBGND must not exceed 0.2

.

DGND, AGND, CPGND, SPKGND, SUBGND

—

Power supply rise time 9,10

9.If the DCVDD rise time exceeds 2 ms, RESET must be asserted (low) during the rise and held asserted until after DCVDD is within the recommended

operating limits.

10.The specified minimum power supply rise times assume a minimum decoupling capacitance of 100 nF per pin. However, Cirrus Logic strongly

advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed. The specified

minimum power supply rise times also assume a maximum PCB inductance of 10 nH between decoupling capacitor and pin.

DCVDD

All other supplies

—

2000

—

s

Operating temperature range

–40

—

ºC

Note: There are no power sequencing requirements; the supplies may be enabled and disabled in any order.

Table 3-4. Analog Input Signal Level—IN1AL, IN1BL, IN1AR, IN1BR, IN2L, IN2R

Test conditions (unless specified otherwise): AVDD = 1.8V; with the exception of the condition noted, the following electrical characteristics are valid

across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Full-scale input signal level (0 dBFS output)

Single-ended PGA input, 0 dB PGA gain

—

0.5

–6

—

VRMS

dBV

Differential PGA input, 0 dB PGA gain

—

VRMS

dBV

Notes:

• The full-scale input signal level is also the maximum analog input level, before clipping occurs.

• The full-scale input signal level changes in proportion with AVDD. For differential input, it is calculated as AVDD/1.8.

• A 1.0VRMS differential signal equates to 0.5VRMS/–6dBV per input.

• A sinusoidal input signal is assumed.

Table 3-5. Analog Input Pin Characteristics

Test conditions (unless specified otherwise): TA = +25ºC; with the exception of the condition noted, the following electrical characteristics are valid across

the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Input resistance

Single-ended PGA input, All PGA gain settings

Differential PGA input, All PGA gain settings

10.5

—



Input capacitance

——

Table 3-6. Analog Input Gain—Programmable Gain Amplifiers (PGAs)

The following electrical characteristics are valid across the full range of recommended operating conditions.

Parameter

Minimum

Typical

Maximum

Units

Minimum programmable gain

—

Maximum programmable gain

—

Programmable gain step size

Guaranteed monotonic

—

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