CS47L35 datasheet(64/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.3 Digital Core

Figure 4-22. Digital-Core Tone Generator

The tone generators can be selected as input to any of the digital mixers or signal-processing functions within the CS47L35

digital core. The hexadecimal numbers in Fig. 4-22 indicate the corresponding x_SRCn setting for selection of that signal

as an input to another digital-core function.

The sample rate for the tone generators is configured using TONE_RATE. See Table 4-21. Note that sample-rate

conversion is required when routing the tone generator outputs to any signal chain that is configured for a different sample

rate.

The tone generators are enabled by setting the TONE1_ENA and TONE2_ENA bits as described in Table 4-17. The

phase relationship is configured using TONE_OFFSET.

The tone generators can also provide a configurable DC signal level, for use as a test signal. The DC output is selected

using the TONEn_OVD bits, and the DC signal amplitude is configured using the TONEn_LVL fields, as described in

Table 4-17.

SYSCLK must be present and enabled before setting the TONEn_ENA bits. The tone generators should be kept disabled

(TONEn_ENA = 0) if SYSCLK is not enabled. See Section 4.16.4 for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

Table 4-17. Tone Generator Control

Label

Default

Description

R32 (0x0020)

Tone_Generator_1

9:8 TONE_

OFFSET[1:0]

Tone Generator Phase Offset. Sets the phase of Tone Generator 2 relative to Tone

Generator 1

00 = 0 degrees (in phase)

01 = 90 degrees ahead

10 = 180 degrees ahead

11 = 270 degrees ahead

5TONE2_

OVD

Tone Generator 2 Override

0 = Disabled (1-kHz tone output)

1 = Enabled (DC signal output)

The DC signal level, when selected, is configured using TONE2_LVL[23:0]

4TONE1_

OVD

Tone Generator 1 Override

0 = Disabled (1-kHz tone output)

1 = Enabled (DC signal output)

The DC signal level, when selected, is configured using TONE1_LVL[23:0]

TONE2_ENA

Tone Generator 2 Enable

0 = Disabled

1 = Enabled

TONE1_ENA

Tone Generator 1 Enable

0 = Disabled

1 = Enabled

R33 (0x0021)

Tone_Generator_2

15:0 TONE1_

LVL[23:8]

0x1000 Tone Generator 1 DC output level

TONE1_LVL[23:8] is coded as 2’s complement. Bits [23:20] contain the integer portion; bits

[19:0] contain the fractional portion.

The digital core 0 dBFS level corresponds to 0x10_0000 (+1) or 0xF0_0000 (–1).

Tone Generator 1 (0x04)

Tone Generator 2 (0x05)

1-kHz

Tone Generator

TONE1_ENA

TONE2_ENA

TONE_OFFSET

TONE_RATE

TONE1_OVD

TONE1_LVL

TONE2_OVD

TONE2_LVL

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