CS47L35 datasheet(59/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.3 Digital Core

4.3.6

Low-/High-Pass Digital Filter (LHPF)

The digital core provides four LHPF processing blocks as shown in Fig. 4-19. A four-input mixer is associated with each

filter. The four input sources are selectable in each case, and independent volume control is provided for each path. Each

LHPF block supports one output.

The LHPF /HPF can be used to remove unwanted out-of-band noise from a signal path. Each filter can be configured either

as a low-pass filter (LPF) or a high-pass filter (HPF).

Figure 4-19. Digital-Core LPF/HPF Blocks

The LHPF1–LHPF4 mixer control fields, shown in Fig. 4-19, are located at register addresses R2304–R2335

(0x0900–0x091F).

The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are

provided in Table 4-7.

The x_SRCn fields select the input sources for the respective LHPF processing blocks. Note that the selected input

sources must be configured for the same sample rate as the LHPF to which they are connected. Sample-rate conversion

functions are available to support flexible interconnectivity; see Section 4.3.14.

The hexadecimal numbers in Fig. 4-19 indicate the corresponding x_SRCn setting for selection of that signal as an input

to another digital-core function.

The LHPF blocks should be kept disabled (LHPFn_ENA = 0) if SYSCLK is not enabled. The x_SRCn fields for all digital

core functions should be held at 0x00 if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting

other values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring SYSCLK while

digital core functions are enabled).

The sample rate for the LHPF function is configured using FX_RATE; see Table 4-21. Note that the EQ, DRC, and LHPF

functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the LHPF

signal paths to any signal chain that is configured for a different sample rate.

The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields

must be cleared before writing a new value to FX_RATE. A minimum delay of 125

s must be allowed between clearing

the x_SRCn fields and writing to FX_RATE. See Table 4-21 for details.

The control registers associated with the LHPF functions are described in Table 4-15.

The cut-off frequencies for the LHPF blocks are set using the coefficients held in registers R3777, R3781, R3785, and

R3789 for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus

Logic’s WISCE evaluation board control software; please contact your Cirrus Logic representative for details.

LHPFnMIX_SRC1

LHPFnMIX_SRC3

LHPFnMIX_SRC4

LHPFnMIX_SRC2

LHPF1 (0x60)

LHPF2 (0x61)

LHPF3 (0x62)

LHPF4 (0x63)

Low-Pass filter (LPF) /

High-Pass filter (HPF)

LHPFnMIX_VOL2

LHPFnMIX_VOL3

LHPFnMIX_VOL4

LHPFnMIX_VOL1

LHPF

…

CS47L35 supports four LHPF blocks, i.e., n = 1–4

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