CS47L35 datasheet(89/300 Pages) CIRRUS

89 / 300 page

DS1085F3

CS47L35

4.5 DSP Peripheral Control

Data to be transmitted is managed using the TX data buffers; the application software must load data into the buffer

registers (MIF1_TX_BYTEx) and then write 1 to the MIF1_TX_DONE bit to commit that data for transmission. The MIF1_

TX_REQUEST bit indicates when the buffer registers are ready for loading new data. Internal buffering of the TX data

enables uninterrupted I2C writes. If new data is not ready for transmission, SCLK halts until the buffer registers have been

filled.

Data received on the interface is managed using the RX data buffers; the MIF1_RX_REQUEST bit indicates when the

buffer registers contain new data. The application software must read the buffer registers (MIF1_RX_BYTEn), and then

write 1 to the MIF1_RX_DONE bit to confirm the data has been read. Internal buffering of the RX data enables

uninterrupted I2C reads. If the buffers are not ready to receive new data, SCLK halts until the buffer registers have been

read.

The master interface divides each I2C transaction into one or more data blocks. The block length is configurable using the

MIF1_TX_BLOCK_LENGTH and MIF1_RX_BLOCK_LENGTH fields. The block length is equal to the number of bytes

transmitted/received for each TX_DONE/RX_DONE action. The maximum block length is 16 bytes, corresponding to the

size of the TX and RX data buffers.

Note: The order in which the data bytes in the TX/RX buffers are transferred depends on the selected MIF1_WORD_

SIZE setting. Correct setting of the word size ensures that each data word is transmitted/received most-significant

byte first.

The Master Interface is configured for Read (RX) or Write (TX) operation using the MIF1_READ_WRITE_SEL bit. Each

I2C transfer is started by writing 1 to the MIF1_START bit. In the case of a Master Write, data must be committed to the

TX data buffers using the TX_DONE bit, to enable the transfer to proceed—note that the first block of transmit data can

be committed to the TX buffers before or after writing to the START bit for the respective transfer.

4.5.1.4 Interrupts and Status Bits

The MIF1_BUSY_STS bit indicates when the master interface is executing an I2C transaction. This bit is set during each

I2C transaction, and cleared on completion. An interrupt event is also triggered on completion of the I2C transfer, if the

corresponding MIF1_DONE_EINTx is unmasked as an input to the IRQ circuit.

Additional status bits are provided to indicate watchdog timeout, loss of bus arbitration, or a NACK error signal received.

Table 4-30 describes these bits.

Note that the MIF done indication is asserted each time an I2C transfer completes, including when an error condition has

occurred. It is recommended that the master interface status bits be checked after each I2C transaction, so corrective

action can be taken when necessary.

The master interface provides inputs to the interrupt control circuit. An interrupt event is triggered on completion of each

TX/RX block, and on completion of the I2C transaction; see Section 4.15.

4.5.1.5 External Connections

The external connections associated with the I2C master interface (MIF) are implemented on multi-function GPIO pins,

which must be configured for the respective MIF functions when required. The MIF1SCLK and MIF1SDA connections are

pin-specific alternative functions available on specific GPIO pins only. See Section 4.14 to configure the GPIO pins for the

MIF operation.

CS47L35 Datasheet(PDF) 89 Page - Cirrus Logic