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CS47L35 Datasheet(PDF) 36 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 36 Page - Cirrus Logic

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36
DS1085F3
CS47L35
4.2 Input Signal Path
4.2.7
Input Signal Path Digital Volume Control
A digital volume control is provided on each input signal path, providing –64 dB to +31.5 dB gain control in 0.5-dB steps.
An independent mute control is also provided for each input signal path.
R788 (0x0314)
IN1R_Control
15
IN1R_HPF
0
Input Path 1 (Right) HPF Enable
0 = Disabled
1 = Enabled
7:1 IN1R_PGA_
VOL[6:0]
0x40 Input Path 1 (Right) PGA Volume (applicable to analog inputs only)
0x00 to 0x3F = Reserved
0x40 = 0 dB
0x41 = 1 dB
0x42 = 2 dB
… (1-dB steps)
0x5F = 31 dB
0x60 to 0x7F = Reserved
R789 (0x0315)
ADC_Digital_
Volume_1R
14:13 IN1R_
SRC[1:0]
00
Input Path 1 (Right) Source
00 = Differential (IN1ARP–IN1ARN)
01 = Single-ended (IN1ARP)
10 = Differential (IN1BRP–IN1BRN)
11 = Single-ended (IN1BRP)
R790 (0x0316)
DMIC1R_Control
5:0 IN1R_
DMIC_
DLY[5:0]
0x00 Input Path 1 (Right) Digital Delay (applicable to digital input only)
LSB = 1 sample, Range is 0 to 63.
(Sample rate is controlled by IN1_OSR.)
R792 (0x0318)
IN2L_Control
15
IN2L_HPF
0
Input Path 2 (Left) HPF Enable
0 = Disabled
1 = Enabled
12:11 IN2_DMIC_
SUP[1:0]
00
Input Path 2 DMIC Reference Select (sets the DMICDAT2 and DMICCLK2 logic levels)
00 = MICVDD
01 = MICBIAS1B
10 = MICBIAS2A
11 = MICBIAS2B
10
IN2_MODE
00
Input Path 2 Mode
0 = Analog input
1 = Digital input
7:1 IN2L_PGA_
VOL[6:0]
0x40 Input Path 2 (Left) PGA Volume (applicable to analog inputs only)
0x00 to 0x3F = Reserved
0x40 = 0 dB
0x41 = 1 dB
0x42 = 2 dB
… (1-dB steps)
0x5F = 31 dB
0x60 to 0x7F = Reserved
R793 (0x0319)
ADC_Digital_
Volume_2L
14:13 IN2L_
SRC[1:0]
00
Input Path 2 (Left) Source
00 = Differential (IN2LP–IN2LN)
01 = Single-ended (IN2LP)
10 = Reserved
11 = Reserved
R794 (0x031A)
DMIC2L_Control
10:8 IN2_
OSR[2:0]
101
Input Path 2 DMIC Oversample Rate (applicable to digital inputs only).
000 = Reserved
001 = Reserved
010 = 384 kHz
011 = 768 kHz
100 = 1.536 MHz
101 = 3.072 MHz
110 = 6.144 MHz
111 = Reserved
If IN2_OSR=010 or 011, the maximum Input Path sample rate (all input paths) is 48 kHz or
96 kHz respectively.
5:0 IN2L_
DMIC_
DLY[5:0]
0x00 Input Path 2 (Left) Digital Delay (applicable to digital input only)
LSB = 1 sample, Range is 0 to 63.
(Sample rate is controlled by IN2_OSR.)
R796 (0x031C)
IN2R_Control
15
IN2R_HPF
0
Input Path 2 (Right) HPF Enable
0 = Disabled
1 = Enabled
7:1 IN2R_PGA_
VOL[6:0]
0x40 Input Path 2 (Right) PGA Volume (applicable to analog inputs only)
0x00 to 0x3F = Reserved
0x40 = 0 dB
0x41 = 1 dB
0x42 = 2 dB
… (1-dB steps)
0x5F = 31 dB
0x60 to 0x7F = Reserved
R797 (0x0319)
ADC_Digital_
Volume_2R
14:13 IN2R_
SRC[1:0]
00
Input Path 2 (Right) Source
00 = Differential (IN2RP–IN2RN)
01 = Single-ended (IN2ARP)
10 = Reserved
11 = Reserved
R798 (0x031E)
DMIC2R_Control
5:0 IN2R_
DMIC_
DLY[5:0]
0x00 Input Path 2 (Right) Digital Delay (applicable to digital input only)
LSB = 1 sample, Range is 0 to 63.
(Sample rate is controlled by IN2_OSR.)
Table 4-3. Input Signal Path Configuration (Cont.)
Register Address
Bit
Label
Default
Description



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