CS47L35 datasheet(51/300 Pages) CIRRUS

51 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

Figure 4-17. Dynamic Range Control (DRC) Block

The DRC1 and DRC2 mixer control fields (see Fig. 4-17) are located at register addresses R2240–R2271

(0x08C0–0x08DF).

The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are

provided in Table 4-7.

The x_SRCn fields select the input sources for the respective DRC processing blocks. Note that the selected input sources

must be configured for the same sample rate as the DRC to which they are connected. Sample-rate conversion functions

are available to support flexible interconnectivity; see Section 4.3.14.

The hexadecimal numbers in Fig. 4-17 indicate the corresponding x_SRCn setting for selection of that signal as an input

to another digital-core function.

The DRC blocks should be kept disabled (DRCnx_ENA = 0) if SYSCLK is not enabled. The x_SRCn fields for all digital

core functions should be held at 0x00 if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting

other values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring SYSCLK while

digital core functions are enabled).

The sample rate for the DRC function is configured using FX_RATE; see Table 4-21. Note that the EQ, DRC, and LHPF

functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the DRC

signal paths to any signal chain that is configured for a different sample rate.

The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields

must be cleared before writing a new value to FX_RATE. A minimum delay of 125

s must be allowed between clearing

the x_SRCn fields and writing to FX_RATE. See Table 4-21 for details.

The DRC functions are enabled using the control registers described in Table 4-11.

DRCnLMIX_VOL2

DRCnLMIX_VOL3

DRCnLMIX_VOL4

DRCnLMIX_VOL1

DRCnLMIX_SRC1

DRCnLMIX_SRC3

DRCnLMIX_SRC4

DRCnLMIX_SRC2

DRC1 Left (0x58)

DRC2 Left (0x5A)

Dynamic Range

Controller

DRCnRMIX_VOL2

DRCnRMIX_VOL3

DRCnRMIX_VOL4

DRCnRMIX_VOL1

DRCnRMIX_SRC1

DRCnRMIX_SRC3

DRCnRMIX_SRC4

DRCnRMIX_SRC2

DRC1 Right (0x59)

DRC2 Right (0x5B)

Dynamic Range

Controller

DRC

…

CS47L35 supports two stereo DRC blocks, i.e., n = 1 or 2

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