CS47L35 datasheet(84/300 Pages) CIRRUS

84 / 300 page

DS1085F3

CS47L35

4.4 DSP Firmware Control

There are eight WDMA (DSP input) and six RDMA (DSP output) channels for each DSP; these are enabled using the

DSPn_WDMA_CHANNEL_ENABLE and DSPn_RDMA_CHANNEL_ENABLE fields. The status of each WDMA channel

is indicated in DSPn_WDMA_ACTIVE_CHANNELS.

The DMA can access the X-data memory or Y-data memory associated with the respective DSP. The applicable memory

is selected using bit [15] of the respective x_START_ADDRESS field for each DMA channel.

The start address of each DMA channel is configured as described in Table 4-26. Note that the required address is defined

relative to the base address of the selected (X-data or Y-data) memory.

The buffer length of the DMA channels is configured using the DSPn_DMA_BUFFER_LENGTH field. The selected buffer

length applies to all enabled DMA channels.

Note that the start-address fields and buffer-length fields are defined in 24-bit DSP data word units. This means that the

LSB of these fields represents one 24-bit DSP memory word. This differs from the CS47L35 register map layout described

in Table 4-23.

The parameters of a DMA channel (i.e., start address or offset address) must not be changed while the respective DMA

is enabled. All of the DMA channels must be disabled before changing the DMA buffer length.

Each DMA channel uses a twin buffer mechanism to support uninterrupted data flow through the DSP. The buffers are

called ping and pong, and are of configurable size, as noted above. Data is transferred to/from each of the buffers in turn.

When the ping input data buffer is full, the DSPn_PING_FULL bit is set, and a DSP start signal is generated. The start

signal from the DMA is typically used to start firmware execution, as noted in Table 4-25. Meanwhile, further DSP input

data fills up the pong buffer.

When the pong input buffer is full, the DSPn_PONG_FULL bit is set, and another DSP start signal is generated. The DSP

firmware must take care to read the input data from the applicable buffer, in accordance with the DSPn_PING_FULL and

DSPn_PONG_FULL status bits.

Twin buffers are also used on the DSP output (RDMA) channels. The output ping buffers are emptied at the same time as

the input ping buffers are filled; the output pong buffers are emptied at the same time that the input pong buffers are filled.

The DSP cores support 24-bit signal processing. Under default conditions, the DSP audio data is in 2’s complement Q3.20

format (i.e., 0xF00000 corresponds to the –1.0 level, and 0x100000 corresponds to the +1.0 level; a sine wave with peak

values of ±1.0 corresponds to the 0 dBFS level). If DSPn_DMA_WORD_SEL is set, audio data is transferred to and from

DSPn in Q0.23 format. The applicable format should be set according to the requirements of the specific DSP firmware.

Note that the DSP cores are optimized for Q3.20 audio data processing; Q0.23 data can be supported, but the firmware

implementation may incur a reduction in power efficiency due to the higher MIPS required for arithmetic operations in

non-native data word format.

The DSPCLK system clock must be configured and enabled before any DMA channel is enabled. The DMA channels

should be kept disabled (DSPn_[WDMA/RDMA]_CHANNEL_ENABLE = 0x00) if DSPCLK is not enabled. See

Section 4.16 for details of the system clocks (including requirements for reconfiguring DSPCLK while DMA channels are

enabled).

The DMA function is an input to the interrupt control circuit—see Section 4.4.4. The respective interrupt event is triggered

if all enabled input (WDMA) channel buffers have been filled and all enabled output (RDMA) channel buffers have been

emptied.

Further details of the DMA are provided in the software programming guide; contact your Cirrus Logic representative if

required.

CS47L35 Datasheet(PDF) 84 Page - Cirrus Logic

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