CS47L35 datasheet(35/300 Pages) CIRRUS

35 / 300 page

DS1085F3

CS47L35

4.2 Input Signal Path

Input paths IN1 and IN2 can be configured as single-ended, differential, or DMIC configuration. The input signal path

configuration is selected using INn_MODE and INnx_SRC.

A configurable high-pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off

frequency is selected using IN_HPF_CUT. The filter can be enabled on each path independently using the INnx_HPF bits.

The analog input signal paths (single-ended or differential) each incorporate a PGA to provide gain in the range 0 dB to

+31 dB in 1-dB steps. Note that these PGAs do not provide pop suppression functions; it is recommended that the gain

should not be adjusted while the respective signal path is enabled.

The analog input PGA gain is controlled using INnL_PGA_VOL and INnR_PGA_VOL. Note that separate volume control

is provided for the left and right channels of each stereo pair.

If the IN1 or IN2 input signal path is configured for DMIC input, the voltage reference for the associated input/output pins

is selectable using the INn_DMIC_SUP fields—each interface may be referenced to MICVDD, or to the MICBIAS1B,

MICBIAS2A, or MICBIAS2B levels. The voltage reference for each digital input path should be set equal to the applicable

power supply of the respective microphones.

When the input signal path is configured for DMIC input, the respective DMICCLKn frequency can be configured using the

INn_OSR bits.

A digital delay may be applied to any of the DMIC input channels. This feature can be used for phase adjustment of any

digital input, including directional control of multiple microphones. The delay is controlled using INnL_DMIC_DLY and

INnR_DMIC_DLY.

The MICVDD voltage is generated by an internal charge pump and LDO regulator. The MICBIASnx outputs are derived

from MICVDD; see Section 4.19.

The input signal paths are configured using the fields described in Table 4-3.

Table 4-3. Input Signal Path Configuration

Bit

Label

Default

Description

R780 (0x030C)

HPF_Control

2:0 IN_HPF_

CUT[2:0]

010

Input Path HPF Select. Controls the cut-off frequency of the input path HPF circuits.

000 = 2.5 Hz

001 = 5 Hz

010 = 10 Hz

011 = 20 Hz

100 = 40 Hz

All other codes are reserved

R784 (0x0310)

IN1L_Control

IN1L_HPF

Input Path 1 (Left) HPF Enable

0 = Disabled

1 = Enabled

12:11 IN1_DMIC_

SUP[1:0]

Input Path 1 DMIC Reference Select (sets the DMICDAT1 and DMICCLK1 logic levels)

00 = MICVDD

01 = MICBIAS1B

10 = MICBIAS2A

11 = MICBIAS2B

IN1_MODE

Input Path 1 Mode

0 = Analog input

1 = Digital input

7:1 IN1L_PGA_

VOL[6:0]

0x40 Input Path 1 (Left) PGA Volume (applicable to analog inputs only)

0x00 to 0x3F = Reserved

0x40 = 0 dB

0x41 = 1 dB

0x42 = 2 dB

… (1-dB steps)

0x5F = 31 dB

0x60 to 0x7F = Reserved

R785 (0x0311)

ADC_Digital_

Volume_1L

14:13 IN1L_

SRC[1:0]

Input Path 1 (Left) Source

00 = Differential (IN1ALP–IN1ALN)

01 = Single-ended (IN1ALP)

10 = Differential (IN1BP–IN1BN)

11 = Single-ended (IN1BP)

R786 (0x0312)

DMIC1L_Control

10:8 IN1_

OSR[2:0]

101

Input Path 1 DMIC Oversample Rate (applicable to digital inputs only).

000 = Reserved

001 = Reserved

010 = 384 kHz

011 = 768 kHz

100 = 1.536 MHz

101 = 3.072 MHz

110 = 6.144 MHz

111 = Reserved

If IN1_OSR=010 or 011, the maximum Input Path sample rate (all input paths) is 48 kHz or

96 kHz respectively.

5:0 IN1L_

DMIC_

DLY[5:0]

0x00 Input Path 1 (Left) Digital Delay (applicable to digital input only)

LSB = 1 sample, Range is 0 to 63.

(Sample rate is controlled by IN1_OSR.)

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