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CS47L35 Datasheet(PDF) 17 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 17 Page - Cirrus Logic |
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17 / 300 page  17 DS1085F3 CS47L35 3 Characteristics and Specifications Table 3-12. Device Reset Thresholds The following electrical characteristics are valid across the full range of recommended operating conditions. Parameter Symbol Minimum Typical Maximum Units AVDD reset threshold VAVDD rising VAVDD falling VAVDD — 1.06 — — 1.66 1.44 V V DCVDD reset threshold VDCVDD rising VDCVDD falling VDCVDD — 0.49 — — 1.04 0.66 V V DBVDD1 Reset threshold VDBVDD1 rising VDBVDD1 falling VDBVDD1 — 1.06 — — 1.66 1.44 V V Note: The reset thresholds are derived from simulations only, across all operational and process corners. Device performance is not assured outside the voltage ranges defined in Table 3-3. Table 3-13. System Clock and Frequency-Locked Loop (FLL) The following timing information is valid across the full range of recommended operating conditions. Parameter Minimum Typical Maximum Units Master clock timing (MCLK1, MCLK2) 1 1.If MCLK1 or MCLK2 is selected as a source for SYSCLK (either directly or via the FLL), the frequency must be within 1% of the SYSCLK_FREQ setting. MCLK cycle time MCLK as input to FLL, FLL1_REFCLK_DIV = 00 MCLK as input to FLL, FLL1_REFCLK_DIV = 01 MCLK as input to FLL, FLL1_REFCLK_DIV = 10 MCLK as input to FLL, FLL1_REFCLK_DIV = 11 MCLK as direct SYSCLK source 74 37 18 12.5 40 — — — — — — — — — — ns ns ns ns ns MCLK duty cycle MCLK as input to FLL MCLK as direct SYSCLK source 80:20 60:40 — — 20:80 40:60 % % Frequency-locked loop (FLL1) FLL input frequency FLL1_REFCLK_DIV = 00 FLL1_REFCLK_DIV = 01 FLL1_REFCLK_DIV = 11 FLL1_REFCLK_DIV = 11 0.032 0.064 0.128 0.256 — — — — 13.5 27 54 80 MHz MHz MHz MHz FLL synchronizer input frequency FLL1_SYNCCLK_DIV = 00 FLL1_SYNCCLK_DIV = 01 FLL1_SYNCCLK_DIV = 10 FLL1_SYNCCLK_DIV = 11 0.032 0.064 0.128 0.256 — — — — 13.5 27 54 80 MHz MHz MHz MHz Internal clocking SYSCLK frequency SYSCLK_FREQ = 000, SYSCLK_FRAC = 0 SYSCLK_FREQ = 000, SYSCLK_FRAC = 1 SYSCLK_FREQ = 001, SYSCLK_FRAC = 0 SYSCLK_FREQ = 001, SYSCLK_FRAC = 1 SYSCLK_FREQ = 010, SYSCLK_FRAC = 0 SYSCLK_FREQ = 010, SYSCLK_FRAC = 1 SYSCLK_FREQ = 011, SYSCLK_FRAC = 0 SYSCLK_FREQ = 011, SYSCLK_FRAC = 1 SYSCLK_FREQ = 100, SYSCLK_FRAC = 0 SYSCLK_FREQ = 100, SYSCLK_FRAC = 1 –1% –1% –1% –1% –1% –1% –1% –1% –1% –1% 6.144 5.6448 12.288 11.2896 24.576 22.5792 49.152 45.1584 98.304 90.3168 +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz DSPCLK frequency 5 — 150 MHz |
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