CS47L35 datasheet(88/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.5 DSP Peripheral Control

The virtual DSP registers are defined at register addresses R4096–R4192 (0x1000–0x1060) in the device register map.

Note that these registers cannot be accessed directly at the addresses shown; they can be only accessed through DSP

firmware code, using the register window function shown in Fig. 4-28. The virtual DSP registers are located at address

0xD000 in the X-data memory map.

4.5 DSP Peripheral Control

The CS47L35 incorporates a suite of DSP peripheral functions that can be integrated together to support the sensor-hub

capability. A master I2C interface is provided for external sensor connectivity. Configurable event log functions provide

multichannel monitoring of internal and external signals. The general-purpose timers provide time-stamp data for the event

logs and support watchdog and other miscellaneous time-based functions. Maskable GPIO provides an efficient

mechanism for multiple DSPs to access the respective input and output signals.

The DSP peripherals are designed to provide a comprehensive sensor-hub capability, operating with a high degree of

autonomy from the host processor.

4.5.1

Master Interface (MIF)

The CS47L35 incorporates an I2C master interface, offering a flexible capability for additional sensor/accessory input.

4.5.1.1 Overview

The master interface (MIF1) can support single- and multiple-master I2C operation up to 1 MHz. The master interface

supports 7- and 10-bit slave addressing modes. Master device arbitration algorithms are implemented, in accordance with

the standard I2C protocol. A watchdog timer is provided for detecting interface error conditions.

The master interface is ideally suited for connection to external sensors such as accelerometers, gyroscopes, and

magnetometers for motion-sensing and navigation applications. Other example accessories include barometers, and

ambient light sensors, for environmental awareness. Flow-control bits for the TX and RX data buffers enable easy

integration with external devices and with internal DSP functions.

4.5.1.2 Clocking Configuration

Clocking for the master interface is derived from DSPCLK, which must be enabled and present when using the MIF

function. Standard I2C bus rates can be supported for typical DSPCLK frequencies using the register settings described

in Table 4-29.

The DSPCLK system clock must be configured and enabled before a Master Interface transaction is scheduled. The

Master Interfaces should be kept idle if DSPCLK is not enabled. See Section 4.16 for details of the system clocks

(including requirements for reconfiguring DSPCLK while DSP peripherals are enabled).

4.5.1.3 Transmit and Receive Data Buffers

The transmit (master write) and receive (master read) actions are each supported by 16-byte data buffers, allowing I2C

transfers of up to 2,097,152 data bytes (2 MB). The number of data bytes transferred in each I2C operation is selected

using MIF1_TX_LENGTH or MIF1_RX_LENGTH.

Table 4-29. Master Interface Clock Configuration

Condition

Value

R262144 (0x40000)

—

0x0000_0006

R262208 (0x40040)

—

0x0000_0000

R262210 (0x40042)

10 kHz I2C Mode

0x01CC_01CC

100 kHz I2C Mode

0x002E_002E

400 kHz I2C Mode

0x000C_000C

1MHz I2C Mode

0x0005_0005

Note: It is assumed that the DSPCLK frequency is one of the nominal (typical) frequencies

specified in Table 4-93.

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