CS47L35 datasheet(95/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.5 DSP Peripheral Control

4.5.2.5 Status Bits

The EVENTLOGn_NOT_EMPTY bit indicates whether the FIFO buffer is empty. When this bit is set, it indicates one or

more new sets of data in the FIFO.

The EVENTLOGn_WMARK_STS bit indicates when the number of FIFO index locations available for new events reaches

a configurable threshold, known as the watermark level. The watermark level is held in the EVENTLOGn_FIFO_WMARK

field.

The EVENTLOGn_FULL bit indicates when the FIFO buffer is full. When this bit is set, it indicates that there are 16 sets

of new event data in the FIFO. Note that this does not mean that a buffer overflow condition has occurred, but further

events are not logged or indicated until the buffer has been cleared.

Note: Following a buffer full condition, the FIFO operation resumes as soon as the RPTR field has been updated to a

new value. Writing the same value to RPTR does not restart the FIFO operation, even if the entire buffer contents

have been read. After all of the required data has been read from the buffer, the RPTR value should be set equal

to the WPTR value; an intermediate (different) value must also be written to the RPTR field in order to clear the

buffer full status and restart the FIFO operation.

4.5.2.6 Interrupts, GPIO, Write Sequencer, and DSP Firmware Control

The control-write sequencer is automatically triggered whenever the NOT_EMPTY status of the event log buffer is

asserted. A different control sequence may be configured for each event logger; see Section 4.18 for further details.

The event log status flags are inputs to the interrupt control circuit and can be used to trigger an interrupt event when the

respective FIFO condition (full, not empty, or watermark level) occurs; see Section 4.15.

The event log status can be output directly on a GPIO pin as an external indication of the event logger; see Section 4.14

to configure a GPIO pin for this function.

The event log NOT_EMPTY status can also be selected as a start trigger for DSP firmware execution; see Section 4.4.

4.5.2.7 Event Logger Control Registers

The event logger control registers are described in Table 4-31.

Table 4-31. Event Logger (EVENTLOGn) Control

Bit

Label

Default

Description

Event Log 1 Base Address = R294912 (0x4_8000)

Event Log 2 Base Address = R295424 (0x4_8200)

Event Log 3 Base Address = R295936 (0x4_8400)

Event Log 4 Base Address = R296448 (0x4_8600)

base address

EVENTLOGn_CONTROL

1EVENTLOGn_RST

Event Log Reset

Write 1 to reset the status outputs and clear the FIFO buffer.

0EVENTLOGn_ENA

Event Log Enable

0 = Disabled

1 = Enabled

Base address +0x04

EVENTLOGn_TIMER_SEL

1:0 EVENTLOGn_TIMER_

SEL[1:0]

Event Log Timer Source Select

00 = Timer 1

01 = Timer 2

10 = Timer 3

11 = Timer 4

Note that the event log must be disabled when updating this

field

Base address +0x0C

EVENTLOGn_FIFO_

CONTROL1

3:0 EVENTLOGn_FIFO_

WMARK[3:0]

0x1

Event Log FIFO Watermark. The watermark status output is

asserted when the number of FIFO locations available for new

events is less than or equal to the FIFO watermark.

Valid from 0 to 15.

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