CS47L35 datasheet(91/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.5 DSP Peripheral Control

R262148 (0x40004)

MIF1_I2C_CONFIG_3

MIF1_NACK_

RESPONSE

Selects the action taken if NACK is received from Slave.

0 = Stop Condition sent.

1 = Stop Condition not sent; next transaction commences with a

Repeated Start.

Note that, if the Stop Condition is not sent, the master retains control of

the bus until a subsequent action is scheduled. The next transaction

commences with a Repeated Start in this case.

MIF1_SCL_MON_ENA

Enables bus monitoring functions on SCLK

0 = Disabled

1 = Enabled

This feature enables support for clock stretching by slave devices, and

enables bus synchronization as part of multimaster operation.

MIF1_RPT_START

Selects the action taken on completion of a bus transaction.

0 = Stop Condition sent.

1 = Stop Condition not sent; next transaction commences with a

Repeated Start.

Note that, if the Stop Condition is not sent, the master retains control of

the bus until a subsequent action is scheduled. The next transaction

commences with a Repeated Start in this case.

MIF1_START_BYTE_

ENA

Selects whether a Start Byte is transmitted before an I2C transaction.

0 = Disabled

1 = Enabled

The Start Byte is a dummy transaction that provides support for bus

devices that use low-frequency polling to detect I2C activity. The Start

Byte, when enabled, is transmitted before the Slave Address bytes. It is

not acknowledged on the bus by any device.

R262152 (0x40008)

MIF1_I2C_CONFIG_5

MIF1_WDT_ENA

Watchdog Timer (WDT) control

0 = Disabled

1 = Enabled

When bus monitoring functions are enabled (MIF1_SCL_MON_

ENA = 1), the watchdog timer is used to detect the SCLK line being

pulled low for a prolonged duration.

R262272 (0x40080)

MIF1_I2C_STATUS_1

MIF1_WDT_TIMEOUT_

STS

Watchdog Timer (WDT) Error Status. This bit, when set, indicates that

the WDT expired during the I2C transaction.

This bit is latched when set; it is only cleared on next I2C transaction.

MIF1_ARBIT_LOST_

STS

Arbitration Error Status. This bit, when set, indicates that arbitration was

lost during the I2C transaction.

This bit is latched when set; it is only cleared on next I2C transaction.

MIF1_NACK_STS

NACK Error Status. This bit, when set, indicates that a NACK Error

signal was received during the I2C transaction.

This bit is latched when set; it is only cleared on next I2C transaction.

R262400 (0x40100)

MIF1_CONFIG_1

MIF1_START

Starts the I2C transaction

Write 1 to start.

R262404 (0x40104)

MIF1_CONFIG_3

17:16 MIF1_WORD_SIZE[1:0]

Selects the data word format. I2C transactions are made up of 1-Byte

data words; the sequence order of these words differs according to the

applicable word format.

Correct setting of the MIF1_WORD_SIZE field ensures that each data

word is transmitted/received as MSB first.

00 = 8-bit (1, 2, 3, 4, 5, 6, 7, 8, etc)

01 = 16-bit (2, 1, 4, 3, 6, 5, 8, 7, etc)

10 = 32-bit (4, 3, 2, 1, 8, 7, 6, 5, etc)

The bracketed numbers describe the order in which applicable MIF1_

[TX|RX]_BYTEx fields are transmitted/received over the I2C interface.

MIF1_READ_WRITE_

SEL

Selects the I2C Command type

0 = Master Write

1 = Master Read

Table 4-30. Master Interface (MIF1) Control (Cont.)

Bit

Label

Default

Description

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