CS47L35 datasheet(16/300 Pages) CIRRUS

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DS1085F3

CS47L35

3 Characteristics and Specifications

Table 3-11. Miscellaneous Characteristics

Test conditions (unless specified otherwise): DBVDD1 = DBVDD2 = CPVDD1 = AVDD = 1.8 V, DCVDD = FLLVDD = CPVDD2 = 1.2 V; MICVDD = 2.5 V

(powered from internal LDO); SPKVDD = 4.2 V; TA = +25ºC; 1 kHz sinusoid signal; Fs = 48 kHz; PGA gain = 0 dB, 24-bit audio data.

Parameter

Min

Typ

Max

Units

Microphone bias

(MICBIAS1A,

MICBIAS1B,

MICBIAS2A,

MICBIAS2B) 1

1.No capacitor on MICBIASn. In Regulator Mode, it is required that VMICVDD – VMICBIAS > 200 mV.

Minimum Bias Voltage 2

Maximum Bias Voltage

Bias Voltage output step size

Bias Voltage accuracy

2.Regulator Mode (MICBn_BYPASS = 0), Load current  1.0 mA.

—

–5%

1.5

2.8

0.1

—

+5%

Bias Current 3

3.Bias current and load capacitance specifications are per MICBIAS generator (MICBIAS1 or MICBIAS2).

Regulator Mode (MICBn_BYPASS = 0), VMICVDD – VMICBIAS >200 mV

Bypass Mode (MICBn_BYPASS = 1)

—

2.4

5.0

Output Noise Density

Regulator Mode (MICBn_BYPASS = 0), MICBn_LVL = 0x4,

Load current = 1 mA, Measured at 1 kHz

—45

—

nV/

Hz

Integrated noise voltage

Regulator Mode (MICBn_BYPASS = 0), MICBn_LVL = 0x4,

Load current = 1 mA, 100 Hz to 7 kHz, A-weighted

—4

—

VRMS

PSRR (DBVDDn, CPVDD1, AVDD), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

105

—

PSRR (DCVDD, FLLVDD, CPVDD2), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

110

—

PSRR (SPKVDD), defined in Table 3-1

100 mV (peak-peak) 217 Hz

100 mV (peak-peak) 10 kHz

—

105

—

Load capacitance 3

Regulator Mode (MICBn_BYPASS = 0), MICBn_EXT_CAP = 0

Regulator Mode (MICBn_BYPASS = 0), MICBn_EXT_CAP = 1

—

0.1

—

1.0

F

Output discharge resistance

MICBnx_ENA = 0, MICBnx_DISCH = 1

—



General-purpose

switch 4

4.The GPSWN pin voltage must not exceed GPSWP + 0.3 V. See Table 3-2 for voltage limits applicable to the GPSWP and GPSWN pins.

Switch resistance

Switch closed, I = 1 mA

Switch open

—

100

—



External

Accessory

Detect

Load impedance detection range:

Detection via HPDETL (ACCDET_MODE = 001)

or HPDETR (ACCDET_MODE = 010)

HP_IMPEDANCE_RANGE = 00

HP_IMPEDANCE_RANGE = 01

HP_IMPEDANCE_RANGE = 10

HP_IMPEDANCE_RANGE = 11

100

1000

—

100

1000

10000



Load impedance detection range:

Detection via MICDET1 or MICDET2 pin (ACCDET_MODE = 100)

400

—

6000



Load impedance detection accuracy

(HP_DACVAL, ACCDET_MODE = 001 or 010)

HP_IMPEDANCE_RANGE = 01 or 10

HP_IMPEDANCE_RANGE = 00 or 11

–5

–10

—

+10

Load impedance detection accuracy (HP_LVL, ACCDET_MODE = 001, 010, or 100)

–20

—

+20

Load impedance detection range—Detection via MICDET1 or

MICDET2 pin (ACCDET_MODE = 000); 2.2 k

 (±2%) MICBIAS

resistor. 5

5.These characteristics assume no other component is connected to MICDETn.

for MICD_LVL[0] = 1

for MICD_LVL[1] = 1

for MICD_LVL[2] = 1

for MICD_LVL[3] = 1

for MICD_LVL[8] = 1

110

210

360

1000

—

180

290

680

30000



Jack-detection input threshold voltage

(JACKDETn)

Detection on JACKDET1, Jack insertion

Detection on JACKDET1, Jack removal

Detection on JACKDET2, Jack insertion

Detection on JACKDET2, Jack removal

—

0.9

1.65

0.27

0.9

—

Pull-up resistance (JACKDETn)—

—



MICVDD Charge

Pump and

Regulator (CP2

and LDO2)

Output voltage

0.9

2.7

3.3

Programmable output voltage step size

LDO2_VSEL = 0x00–0x14 (0.9–1.4V )

LDO2_VSEL = 0x14 to 0x27 (1.4 V–3.3 V)

—

100

—

Maximum output current

—

Start-up time

4.7

F on MICVDD —

1.5

2.5

Frequency-Lock

ed Loop (FLL1)

Output frequency

FLL output as SYSCLK source

FLL output as DSPCLK source

135

—

98.3

150

MHz

Lock Time

FREF =32kHz, FOUT (DSPCLK source) = 147.456 MHz

FREF =12MHz, FOUT (DSPCLK source) = 147.456 MHz

—

RESET pin input RESET input pulse width 6

6.To trigger a hardware reset, the RESET input must be asserted for longer than this duration.

1—

—

s

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