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CS47L35 Datasheet(PDF) 78 Page - Cirrus Logic |
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CS47L35 Datasheet(HTML) 78 Page - Cirrus Logic |
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78 / 300 page  78 DS1085F3 CS47L35 4.4 DSP Firmware Control DSP firmware can be configured using software packages provided by Cirrus Logic. A software programming guide can also be provided to assist users in developing their own software algorithms—please contact your Cirrus Logic representative for further information. To use the DSP blocks, the required firmware configuration must first be loaded onto the device by writing the appropriate files to the CS47L35 register map. The firmware configuration comprises program, data, and coefficient content. In some cases, the coefficient content must be derived using tools provided in the WISCE evaluation board control software. Details of the DSP firmware memory registers are provided in Section 4.4.1. Note that the WISCE evaluation board control software provides support for easy loading of program, data, and coefficient content onto the CS47L35. Please contact your Cirrus Logic representative for more details of the WISCE evaluation board control software. After loading the DSP firmware, the DSP functions must be enabled using the associated control fields. The audio signal paths to and from the DSP processing blocks are configured as described in Section 4.3. Note that the DSP firmware must be loaded and enabled before audio signal paths can be enabled. 4.4.1 DSP Firmware Memory and Register Mapping The DSP firmware memory is programmed by writing to the registers referenced in Table 4-23. Note that clocking is not required for access to the firmware registers by the host processor. The CS47L35 program, data, and coefficient register memory space is described in Table 4-23. The full register map listing is provided in Section 6. The shared DSP2/DSP3 memory space is implemented at two different register address locations; reading or writing at either address accesses the same memory data. If multiple DSPs write to a shared-memory address at the same time, the address at which the collision occurred is reported in the DSP2_DUALMEM_COLLISION_ADDR and DSP3_DUALMEM_COLLISION_ADDR fields. Note that these fields are coded in 24-bit DSP data word units, and are defined relative to the base address of the shared-memory area. The DSP2_DUALMEM_COLLISION_ADDR and DSP3_DUALMEM_COLLISION_ADDR fields provide the same information. The DSP memory controller provides an input to the interrupt control circuit. An interrupt event is triggered if a memory collision occurs. Note that the DSP software should be written to ensure this never happens; the interrupt is intended for development purposes only. See Section 4.15 for details of the interrupt-event handling. The program firmware parameters are formatted as 40-bit words. For this reason, 3 x 32-bit register addresses are required for every 2 x 40-bit words. The X-memory on each DSP supports read/write access to all register fields throughout the device, including the codec control registers, and the firmware memory of all of the integrated DSP cores. Access to the register address space is supported using a number of register windows within the X-memory on each DSP. Table 4-23. DSP Program, Data, and Coefficient Registers DSP Number Description Register Address Number of Registers DSP Memory Size DSP1 Program memory 0x08_0000–0x08_5FFE 12288 8k x 40-bit words X-Data memory 0x0A_0000–0x0A_7FFE 16384 16k x 24-bit words Y-Data memory 0x0C_0000–0x0C_1FFE 4096 4k x 24-bit words Coefficient memory 0x0E_0000–0x0E_1FFE 4096 4k x 24-bit words DSP2 Program memory 0x10_0000–0x10_EFFE 30720 20k x 40-bit words X-Data memory 0x12_0000–0x12_BFFE 24576 24k x 24-bit words X-Data memory (Shared DSP2/DSP3) 0x13_6000–0x13_7FFE 4096 4k x 24-bit words Y-Data memory 0x14_0000–0x14_BFFE 24576 24k x 24-bit words Coefficient memory 0x16_0000–0x16_1FFE 4096 4k x 24-bit words DSP3 Program memory 0x18_0000–0x18_EFFE 30720 20k x 40-bit words X-Data memory 0x1A_0000–0x1B_1FFE 36864 36k x 24-bit words X-Data memory (Shared DSP2/DSP3) 0x1B_6000–0x1B_7FFE 4096 4k x 24-bit words Y-Data memory 0x1C_0000–0x1C_BFFE 24576 24k x 24-bit words Coefficient memory 0x1E_0000–0x1E_1FFE 4096 4k x 24-bit words |
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