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CS47L35 Datasheet(PDF) 288 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 288 Page - Cirrus Logic

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288
DS1085F3
CS47L35
6 Register Map
R329746
(50812h)
RA_TIMER1_Thread_
Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER1_IN_USE_SET [4:0]
R329748
(50814h)
RA_TIMER1_Thread_
Ctrl_3
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER1_IN_USE_CLR [4:0]
R329750
(50816h)
RA_TIMER1_Thread_
Ctrl_4
0
0
0
000
000
00
000
00
00000001h
0
0
0
000
000
00
000
0
RA_
TIMER1_
CAP_EVT
R329752
(50818h)
RA_TIMER1_Thread_
Ctrl_Debug_1
RA_TIMER1_IN_USE_DBG0 [31:16]
00000000h
RA_TIMER1_IN_USE_DBG0 [15:0]
R329760
(50820h)
RA_TIMER2_Thread_
Ctrl_1
0
0
0
000
000
00
000
00
00000000h
RA_
TIMER2_
IN_USE_
STS
RA_
TIMER2_
SHARE
0
000
000
00
RA_TIMER2_OWNER [4:0]
R329762
(50822h)
RA_TIMER2_Thread_
Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER2_IN_USE_SET [4:0]
R329764
(50824h)
RA_TIMER2_Thread_
Ctrl_3
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER2_IN_USE_CLR [4:0]
R329766
(50826h)
RA_TIMER2_Thread_
Ctrl_4
0
0
0
000
000
00
000
00
00000001h
0
0
0
000
000
00
000
0
RA_
TIMER2_
CAP_EVT
R329768
(50828h)
RA_TIMER2_Thread_
Ctrl_Debug_1
RA_TIMER2_IN_USE_DBG0 [31:16]
00000000h
RA_TIMER2_IN_USE_DBG0 [15:0]
R329776
(50830h)
RA_TIMER3_Thread_
Ctrl_1
0
0
0
000
000
00
000
00
00000000h
RA_
TIMER3_
IN_USE_
STS
RA_
TIMER3_
SHARE
0
000
000
00
RA_TIMER3_OWNER [4:0]
R329778
(50832h)
RA_TIMER3_Thread_
Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER3_IN_USE_SET [4:0]
R329780
(50834h)
RA_TIMER3_Thread_
Ctrl_3
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER3_IN_USE_CLR [4:0]
R329782
(50836h)
RA_TIMER3_Thread_
Ctrl_4
0
0
0
000
000
00
000
00
00000001h
0
0
0
000
000
00
000
0
RA_
TIMER3_
CAP_EVT
R329784
(50838h)
RA_TIMER3_Thread_
Ctrl_Debug_1
RA_TIMER3_IN_USE_DBG0 [31:16]
00000000h
RA_TIMER3_IN_USE_DBG0 [15:0]
R329792
(50840h)
RA_TIMER4_Thread_
Ctrl_1
0
0
0
000
000
00
000
00
00000000h
RA_
TIMER4_
IN_USE_
STS
RA_
TIMER4_
SHARE
0
000
000
00
RA_TIMER4_OWNER [4:0]
R329794
(50842h)
RA_TIMER4_Thread_
Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER4_IN_USE_SET [4:0]
R329796
(50844h)
RA_TIMER4_Thread_
Ctrl_3
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_TIMER4_IN_USE_CLR [4:0]
R329798
(50846h)
RA_TIMER4_Thread_
Ctrl_4
0
0
0
000
000
00
000
00
00000001h
0
0
0
000
000
00
000
0
RA_
TIMER4_
CAP_EVT
R329800
(50848h)
RA_TIMER4_Thread_
Ctrl_Debug_1
RA_TIMER4_IN_USE_DBG0 [31:16]
00000000h
RA_TIMER4_IN_USE_DBG0 [15:0]
R330752
(50C00h)
RA_DSPGP_SET_
Thread_Ctrl_1
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
0
RA_DSPGP_SET_STS [3:0]
R330756
(50C04h)
RA_DSPGP_SET_
Thread_Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
0
0
0
0
0
0
0
0
0
RA_DSPGP_SET_SHARE_STS [3:0]
R330760
(50C08h)
RA_DSPGP_SET_
Thread_Ctrl_3
0
0
0
000
000
00
000
00
00000004h
0
0
0
000
000
0
RA_DSPGP_SET_NUM [5:0]
R330768
(50C10h)
RA_DSPGP_SET1_
Thread_Ctrl_1
0
0
0
000
000
00
000
00
00000000h
RA_
DSPGP_
SET1_IN_
USE_STS
RA_
DSPGP_
SET1_
SHARE
0
000
000
00
RA_DSPGP_SET1_OWNER [4:0]
R330770
(50C12h)
RA_DSPGP_SET1_
Thread_Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_DSPGP_SET1_IN_USE_SET [4:0]
R330772
(50C14h)
RA_DSPGP_SET1_
Thread_Ctrl_3
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_DSPGP_SET1_IN_USE_CLR [4:0]
R330776
(50C18h)
RA_DSPGP_SET1_
Thread_Ctrl_Debug_1
RA_DSPGP_SET1_IN_USE_DBG0 [31:16]
00000000h
RA_DSPGP_SET1_IN_USE_DBG0 [15:0]
R330784
(50C20h)
RA_DSPGP_SET2_
Thread_Ctrl_1
0
0
0
000
000
00
000
00
00000000h
RA_
DSPGP_
SET2_IN_
USE_STS
RA_
DSPGP_
SET2_
SHARE
0
000
000
00
RA_DSPGP_SET2_OWNER [4:0]
R330786
(50C22h)
RA_DSPGP_SET2_
Thread_Ctrl_2
0
0
0
000
000
00
000
00
00000000h
0
0
0
000
000
00
RA_DSPGP_SET2_IN_USE_SET [4:0]
Table 6-2. Register Map Definition—32-bit region (Cont.)
Register
Name
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
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