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ADV7321 Datasheet(PDF) 34 Page - Analog Devices

Part # ADV7321
Description  Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
PDF  88 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7321 Datasheet(HTML) 34 Page - Analog Devices

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ADV7320/ADV7321
Rev. 0 | Page 34 of 88
Table 17. Registers 0x4A to 0x58
SR7–
SR0
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset
Value
0
Slave mode.
SD Slave/Master
Mode
1
Master mode.
0x08
0
0
Mode 0.
0
1
Mode 1.
1
0
Mode 2.
SD Timing Mode
1
1
Mode 3.
0
Enabled.
SD BLANK Input
1
Disabled.
0
0
No delay.
0
1
2 clk cycles.
1
0
4 clk cycles.
SD Luma Delay
1
1
6 clk cycles.
0
−40 IRE.
SD Min. Luma
Value
1
−7.5 IRE.
0x4A
SD Timing
Register 0
SD Timing Reset
x
0
0
0
0
0
0
0
A low-high-low transition will
reset the internal SD timing
counters.
0
0
Ta = 1 clk cycle.
0
1
Ta = 4 clk cycles.
1
0
Ta = 16 clk cycles.
SD HSYNC Width
1
1
Ta = 128 clk cycles.
0x00
0
0
Tb = 0 clk cycle.
0
1
Tb = 4 clk cycles.
1
0
Tb = 8 clk cycles.
SD HSYNCto
VSYNC Delay
1
1
Tb = 18 clk cycles.
x
0
Tc = Tb.
SD HSYNC to VSYNC
Rising Edge Delay
(Mode 1 Only)
x
1
Tc = Tb + 32 µs.
0
0
1 clk cycle.
0
1
4 clk cycles.
1
0
16 clk cycles.
VSYNC Width
(Mode 2 Only)
1
1
128 clk cycles.
0
0
0 clk cycles.
0
1
1 clk cycle.
1
0
2 clk cycles.
0x4B
SD Timing
Register 1
HSYNC to Pixel
Data Adjust
1
1
3 clk cycles.
0x4C
SD FSC Register 01
x
x
x
x
x
x
x
x
Subcarrier Frequency Bits 7 to 0.
0x1E1
0x4D
SD FSC Register 1
x
x
x
x
x
x
x
x
Subcarrier Frequency Bits 15 to 8.
0x7C
0x4E
SD FSC Register 2
x
x
x
x
x
x
x
x
Subcarrier Frequency Bits 23 to 16.
0xF0
0x4F
SD FSC Register 3
x
x
x
x
x
x
x
x
Subcarrier Frequency Bits 31 to 24.
0x21
0x50
SD FSC Phase
x
x
x
x
x
x
x
x
Subcarrier Phase Bits 9 to 2.
0x00
0x51
SD Closed
Captioning
Extended Data on
Even Fields
x
x
x
x
x
x
x
x
Extended Data Bits 7 to 0.
0x00
0x52
SD Closed
Captioning
Extended Data on
Even Fields
x
x
x
x
x
x
x
x
Extended Data Bits 15 to 8.
0x00
0x53
SD Closed
Captioning
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bits 7 to 0.
0x00
0x54
SD Closed
Captioning
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bits 15 to 8.
0x00
0x55
SD Pedestal
Register 0
Pedestal on Odd
Fields
17
16
15
14
13
12
11
10
Setting any of these bits to 1 will
disable pedestal on the line num-
ber indicated by the bit settings.
0x00
0x56
SD Pedestal
Register 1
Pedestal on Odd
Fields
25
24
23
22
21
20
19
18
0x00
0x57
SD Pedestal
Register 2
Pedestal on Even
Fields
17
16
15
14
13
12
11
10
0x00
0x58
SD Pedestal
Register 3
Pedestal on Even
Fields
25
24
23
22
21
20
19
18
0x00
1 For precise NTSC Fsc, this register should be programmed to 0x1F.
LINE 313
LINE 314
LINE 1
tB
tA
tC
HSYNC
VSYNC
Figure 48. Timing Register 1 in PAL Mode



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