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ADV7321 Datasheet(PDF) 74 Page - Analog Devices |
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ADV7321 Datasheet(HTML) 74 Page - Analog Devices |
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74 / 88 page ![]() ADV7320/ADV7321 Rev. 0 | Page 74 of 88 MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 1) The ADV7320/ADV7321 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on S_HSYNC, the V bit is output on S_BLANK, and the F bit is output on S_VSYNC. 522 523 524 525 8 9 10 11 20 21 22 DISPLAY DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD H V F 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK H V F 7 6 5 4 3 2 1 Figure 110. SD Master Mode 0, NTSC |
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