ADV7321 datasheet(43/88 Pages) AD

43 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 43 of 88

HD TIMING RESET

A timing reset is achieved by toggling the HD timing reset control

bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal

and vertical counters remain reset. When this bit is set back to 0,

the internal counters resume counting.

The minimum time the pin must be held high is one clock

cycle; otherwise, this reset signal might not be recognized. This

timing reset applies to the HD timing counters only.

SD REAL-TIME CONTROL, SUBCARRIER RESET,

AND TIMING RESET

[Subaddress 0x44, Bits 2 and 1]

Together with the RTC_SCR_TR pin and SD Mode Register 3

[Address 0x44, Bits 1 and 2], the ADV7320/ADV7321 can be

used in (a) timing reset mode, (b) subcarrier phase reset mode,

or (c) RTC mode.

A timing reset is achieved in a low-to-high transition

on the RTC_SCR_TR pin (Pin 31). In this state, the

horizontal and vertical counters remain reset. Upon

releasing this pin (set to low), the internal counters

resume counting, starting with Field 1, and the

subcarrier phase is reset.

The minimum time the pin must be held high is one

clock cycle; otherwise, this reset signal might not be

recognized. This timing reset applies to the SD timing

counters only.

In subcarrier phase reset, a low-to-high transition on

the RTC_SCR_TR pin (Pin 31) resets the subcarrier

phase to zero on the field following the subcarrier

phase reset when the SD RTC/TR/SCR control bits at

Address 0x44 are set to 01.

This reset signal must be held high for a minimum of

one clock cycle.

Because the field counter is not reset, it is

recommended that the reset signal is applied in Field 7

(PAL) or Field 3 (NTSC). The reset of the phase will

then occur on the next field, i.e., Field 1, lined up

correctly with the internal counters. The field count

number of the active field.

In RTC mode, the ADV7320/ADV7321 can be used to

lock to an external video source. The real-time control

mode allows the ADV7320/ADV7321 to automatically

alter the subcarrier frequency to compensate for line

length variations. When the part is connected to a

device, such as an ADV7183A video decoder (see

Figure 62), that outputs a digital data stream in the

RTC format, the part will automatically change to the

compensated subcarrier frequency on a line-by-line

basis. This digital data stream is 67 bits wide and the

subcarrier is contained in Bits 0 to 21. Each bit is two

clock cycles long. Write 0x00 into all four subcarrier

frequency registers when this mode is used.

DISPLAY

NO TIMING RESET APPLIED

TIMING RESET APPLIED

START OF FIELD 4 OR 8

FSC PHASE = FIELD 4 OR 8

FSC PHASE = FIELD 1

TIMING RESET PULSE

307

310

307

12345

313

320

DISPLAY

START OF FIELD 1

Figure 60. Timing Reset Timing Diagram

ADV7321 Datasheet(PDF) 43 Page - Analog Devices

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