ADV7321 datasheet(80/88 Pages) AD

80 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 80 of 88

MODE 3—MASTER/SLAVE OPTION

(TIMING REGISTER 0 TR0 =

X X X X X 1 1 0 OR X X X X X 1 1 1)

In this mode, the ADV7320/ADV7321 accept or generate hori-

zontal sync and odd/even field signals. When HSYNC is high, a

transition of the field input indicates a new frame, i.e., vertical

retrace. The BLANK signal is optional. When the BLANK input

is disabled, ADV7320/ADV7321 automatically blank all

normally blank lines as per CCIR-624. HSYNC, BLANK, and

VSYNC are output in master mode and input in slave mode on

S_VSYNC, S_BLANK, and S_VSYNC, respectively.

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

Figure 120. SD Timing Mode 3 (NTSC)

622

623

624

625

621

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

320

HSYNC

BLANK

HSYNC

BLANK

Figure 121. SD Timing Mode 3 (PAL)

ADV7321 Datasheet(PDF) 80 Page - Analog Devices

ADV7321 Datasheet(HTML) 80 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL