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ADV7321 Datasheet(PDF) 14 Page - Analog Devices

Part # ADV7321
Description  Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
PDF  88 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV7321 Datasheet(HTML) 14 Page - Analog Devices

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ADV7320/ADV7321
Rev. 0 | Page 14 of 88
Y0
Y1
Y2
Y3
b
a
Cb1
Cr1
Cr0
Cb0
c
Y OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y9–Y0
C9–C0
a AND b AS PER RELEVANT STANDARD
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATION
SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC IN TO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 15. HD 4:2:2 Input Timing Diagram
Y9–Y0
Cb
Y
Cr
Y
b
a
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
P_HSYNC
P_VSYNC
P_BLANK
Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram



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