ADV7321 datasheet(39/88 Pages) AD

39 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 39 of 88

optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and

S_BLANK. HD syncs are input on Pins P_VSYNC, P_HSYNC,

and P_BLANK.

CLKIN_A

CLKIN_B

MPEG2

DECODER

27MHz

YCrCb

INTERLACED TO

PROGRESSIVE

CrCb

27MHz

S[9:0]

C[9:0]

Y[9:0]

ADV7320/

ADV7321

S_VSYNC,

S_HSYNC,

S_BLANK

P_VSYNC,

P_HSYNC,

P_BLANK

Figure 51. Simultaneous PS and SD Input

CLKIN_A

CLKIN_B

SDTV

DECODER

27MHz

YCrCb

CrCb

74.25MHz

1080i

720p

1035i

S[9:0]

C[9:0]

Y[9:0]

ADV7320/

ADV7321

HDTV

DECODER

S_VSYNC,

S_HSYNC,

S_BLANK

P_VSYNC,

P_HSYNC,

P_BLANK

Figure 52. Simultaneous HD and SD Input

In simultaneous SD/HD input mode, if the two clock phases

differ by less than 9.25 ns or more than 27.75 ns, the clock align

bit [Address 0x01, Bit 3] must be set accordingly. If the

application uses the same clock source for both SD and PS, the

clock align bit must be set because the phase difference between

both inputs is less than 9.25 ns.

CLKIN_A

CLKIN_B

tDELAY < 9.25ns OR

tDELAY > 27.75ns

Figure 53. Clock Phase with Two Input Clocks

PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE)

OR 54 MHZ

Address[0x01]: Input Mode 100 or 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or

54 MHz. The input data is interleaved onto a single 8-/10-bit

bus and is input on Pins Y9 to Y0. When a 27 MHz clock is

supplied, the data is clocked in upon the rising and falling edges

of the input clock, and the clock edge bit [Address 0x01, Bit 1]

must be set accordingly.

Table 22 provides an overview of all possible input configurations.

Figure 54, Figure 55, and Figure 56 show the possible conditions:

Cb data on the rising edge, and Y data on the rising edge.

3FF

Cr0

CLKIN_B

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.

Y9–Y0

Cb0

Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

3FF

Cb0

Cr0

CLKIN_B

Y9–Y0

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.

Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

PIXEL INPUT

DATA

3FF

Cb0

Cr0

CLKIN_B

WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.

Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

MPEG2

DECODER

CLKIN_A

Y[9:0]

INTERLACED

PROGRESSIVE

YCrCb

27MHz OR 54MHz

YCrCb

ADV7320/

ADV7321

P_VSYNC,

P_HSYNC,

P_BLANK

Figure 57. 10-Bit PS at 27 MHz or 54 MHz

ADV7321 Datasheet(PDF) 39 Page - Analog Devices

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