ADV7321 datasheet(72/88 Pages) AD

72 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 72 of 88

The register settings in Table 41 are used to generate an SD

NTSC CVBS output on DAC A, S-video on DACs B and C, and

YPrPb on DACs D, E, and F. Upon power-up, the subcarrier

registers are programmed with the appropriate values for

NTSC. All other registers are set as normal/default.

Table 41. NTSC Test Pattern Register Writes

Subaddress

0x00

0xFC

0x40

0x10

0x42

0x40

0x44

0x40 (internal test pattern on)

0x4A

0x08

For PAL CVBS output on DAC A, the same settings are used,

except that Subaddress 0x40 is programmed to 0x11 and the FSC

registers are programmed as shown in Table 42.

Table 42. PAL FSC Register Writes

Subaddress

Description

0x4C

FSC0

0xCB

0x4D

FSC1

0x8A

0x4E

FSC2

0x09

0x4F

FSC3

0x2A

Note that when programming the FSC registers, the user must

write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full

FSC value to be written is only accepted after the FSC3 write is

complete.

The register settings in Table 43 are used to generate a 525p

hatch pattern on DAC D, E, and F. All other registers are set as

normal/default.

Table 43. 525p Test Pattern Register Writes.

Subaddress

Ox00

0xFC

0x01

0x10

0x00

0x11

0x05

0x16

0xA0

0x17

0x80

0x18

0x80

For 625p hatch pattern on DAC D, the same register settings are

used except that Subaddress 0x10 = 0x18.

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