ADV7321 datasheet(44/88 Pages) AD

44 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 44 of 88

NO FSC RESET APPLIED

FSC PHASE = FIELD 4 OR 8

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

FSC RESET APPLIED

FSC RESET PULSE

FSC PHASE = FIELD 1

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

Figure 61. Subcarrier Reset Timing Diagram

LCC1

GLL

P19–P10

ADV7183A

VIDEO

DECODER

COMPOSITE

VIDEO1

CLKIN_A

RTC_SCR_TR

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

Y9–Y0/S9–S05

RTC

LOW

H/L TRANSITION

COUNT START

128

TIME SLOT 01

14 BITS

SUBCARRIER

PHASE

FSC PLL INCREMENT2

VALID

SAMPLE

INVALID

SAMPLE

6768

4 BITS

RESERVED

SEQUENCE

BIT3

RESET

BIT4

RESERVED

ADV7320/

ADV7321

NOTES

1i.e., VCR OR CABLE

2FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS

OF THE ADV7320/ADV7321.

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

4RESET ADV7320/ADV7321 DDS

5SELECTED BY REGISTER ADDRESS 0x01 BIT 7

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

Figure 62. RTC Timing and Connections

ADV7321 Datasheet(PDF) 44 Page - Analog Devices

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