ADV7321 datasheet(28/88 Pages) AD

28 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 28 of 88

Table 10. Register 0x12

SR7–

SR0

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

0 clk cycles

0x00

1 clk cycles

2 clk cycles

3 clk cycles

HD Y Delay with Respect

to Falling Edge of HSYNC

4 clk cycles

0 clk cycles

1 clk cycle

2 clk cycles

3 clk cycles

HD Color Delay with

Respect to Falling Edge of

HSYNC

4 clk cycles

Disabled

HD CGMS

Enabled

Disabled

0x12

HD Mode

HD CGMS CRC

Enabled

Table 11. Registers 0x13 to 0x14

SR7–

SR0

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

Cb after falling edge of HSYNC.

0x4C

HD Cr/Cb Sequence

Cr after falling edge of HSYNC.

Reserved

0 must be written to this bit.

8-bit input.

HD Input Format

10-bit input.

Disabled.

Sinc Filter on DAC D, E, F

Enabled.

Reserved

0 must be written to this bit.

Disabled.

HD Chroma SSAF

Enabled.

4:4:4

HD Chroma Input

4:2:2

Disabled.

0x13

HD Mode

HD Double Buffering

Enabled.

HD Timing Reset

A low-high-low transition

resets the internal HD timing

counters.

0x00

HD Hsync Generation1

HD Vsync Generation1

Refer to the / Output Control

section.

BLANK active high.

HD Blank Polarity

BLANK active low.

Macrovision disabled.

HD Macrovision for 525p

and 625p

Macrovision enabled.

Reserved

0 must be written to these bits.

0 = field input.

HD VSYNC/Field Input

1 = VSYNC input.

Update field/line counter.

0x14

HD Mode

Horizontal/Vertical

Counters2

Field/line counter free running.

1 Used in conjunction with HD_SYNC in Register 0x02, Bit 7 set to 1.

2 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

ADV7321 Datasheet(PDF) 28 Page - Analog Devices

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