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AMD-766 Datasheet(PDF) 18 Page - Advanced Micro Devices

Part # AMD-766
Description  Peripheral Bus Controller
PDF  96 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-766 Datasheet(HTML) 18 Page - Advanced Micro Devices

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Preliminary Information
23167B – March 2001
AMD-766
TM Peripheral Bus Controller Data Sheet
18
4.3.4
Interrupt Controllers
The IC includes two interrupt controllers: the legacy PIC and an IOAPIC. Interrupt sources are routed to the
interrupt controllers as shown in the following diagram.
IOAPIC
24
redirection
registers
APIC interrupt
message bus
SCI
Interrupt pins
to the host
Legacy
PIC
GPIO[17, 16, 3, 2 ]
Interrupt
routing
logic
IRQ pins, TCO,
PNPIRQ[2:0],
serial IRQ
PIRQ[D:A]#
INTR
NMI, INIT
SMI
4.3.4.1
Interrupt Routing Logic
Vectored interrupt requests are routed to the legacy
PIC and APIC as shown. The interrupt signals to the
PIC may be either rising-edge triggered or active-low
level triggered. It is expected that edge-triggered
interrupts such as IRQ14 from the IDE controller rise
into the PIC to indicate the presence of an interrupt.
Conversely, level-sensitive interrupts are low into the
PIC to indicate the presence of an interrupt. Edge and
level sensitivity for each IRQ are programmed into the
PIC through PORT4D0.
PIRQ[D:A]#
PNPIRQ[2:0]
IRQx (from ISA bus)
Serial IRQs
PIC
IOAPIC
PORTD0
USB_INT
SCI_IRQ
PIC_IRQx
Interrupt
Routing
Logic
The internal USB interrupt signal drives the PIRQD# pin low as an output; when the USB interrupt is deasserted,
PIRQD# is left in the high impedance state. So the USB interrupt is wired-ORed into the active state with external
interrupts on PIRQD#. The result enters the IC and goes to the interrupt routing logic.
The following are the interrupt routing logic equations:



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