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AMD-766 Datasheet(PDF) 93 Page - Advanced Micro Devices

Part # AMD-766
Description  Peripheral Bus Controller
PDF  96 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-766 Datasheet(HTML) 93 Page - Advanced Micro Devices

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Preliminary Information
23167B – March 2001
AMD-766
TM Peripheral Bus Controller Data Sheet
93
9
Test
The IC includes five NAND trees for continuity testing. It is also possible to place all the IO pins into the high-
impedance state. These modes are entered by asserting the following pins:
Mode
Equation to enable mode
High Impedance ~TEST# & PWRGD & ~PGNT# & ~SERR#
NAND Tree
~TEST# & PWRGD & ~PGNT# &
SERR#
9.1
High Impedance Mode
When in high impedance mode, all the signals on the IC are placed into the high impedance state.
9.2
NAND Tree Mode
There are five NAND trees in the IC. The following diagram shows how these are connected, using example signals
from NAND tree 1.
NAND Tree Mode
To BCLK pin
BCLK signal
…
…
LDRQ1#
GPIO17
SA0
SA1
VDD
1
0
When in NAND tree mode, the five NAND tree output signals are enabled and the remaining signals are in high-
impedance mode. The following pins are not part of the NAND tree: RTCX_IN, RTCX_OUT, PWRGD, PCLK,
TEST#, PGNT#, and SERR#.
The following tables provide the signal order and output signal for each NAND tree.
NAND tree 1: output signal BCLK.
1
SA1
11 SD2
21 LA19
31 CPUSLEEP# 41 LAD1
51 SA12
2
SA0
12 IRQ10
22 GPIO21
32 KA20G
42 GPIO2
52 LFRAME#
3
GPIO17
13 LA21
23 SA16
33 MEMR#
43 PRDY
53 GPIO31
4
SD4
14 SD1
24 IRQ15
34 MEMW#
44 LAD2
54 SA10
5
GPIO19
15 SD0
25 LA18
35 KBRC#
45 GPIO29
55 SA11
6
LA23
16 IRQ11
26 GPIO20
36 GPIO9
46 EKIRQ1
56 LDRQ0#
7
SD3
17 LA20
27 IOW#
37 LAD0
47 SA13
57 GPIO30
8
GPIO18
18 IOCHRDY
28 IRQ14
38 STRAPL2
48 LAD3
58 SA9
9
LA22
19 GPIO25
29 LA17
39 SA14
49 GPIO28
59 LDRQ1#
10
EKIRQ12
20 IRQ12
30 IOR#
40 SA15
50 GPIO23



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