AMD-766 datasheet(38/96 Pages) AMD

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Preliminary Information

23167B – March 2001

AMD-766

TM Peripheral Bus Controller Data Sheet

C0A4B: IOAPIC Configuration Register

Configuration space; function 0; offset: 4Bh Default: 00h Read-write.

7:5

4:3

210

Reserved

APICCKS[1:0]

SCI2IOA

SMI2IOA

APICEN

APICEN. IOAPIC enable. 0=Accesses to the IOAPIC memory space are routed to the ISA/LPC bus and the

interrupt message bus is not used. 1=The IOAPIC is enabled, accesses to the IOAPIC memory space are not reflected

on the ISA/LPC bus, and the interrupt message bus is used to transmit IOAPIC interrupts.

SMI2IOA. SMI to IOAPIC redirection register 23. 1=The SMI output of the power management logic is routed

through redirection register 23 of the IOAPIC; the SMI# pin is never asserted. 0=IRQ23 of the IOAPIC is driven

with the output of the GPIO17 input path (regardless as to the state of PMD1) and the SMI# pin is controlled by the

IC.

SCI2IOA. SCI to IOAPIC redirection register 22. 1=The SCI output of the power management logic is routed

through redirection register 22 of the IOAPIC; C3A42[SCISEL] disabled. 0=IRQ22 of the IOAPIC is driven with

the output of the GPIO16 input path (regardless as to the state of PMD0); C3A42[SCISEL] functions normally.

APICCKS. APIC clock select. Selects the source and frequency of the PICCLK as follows:

APICCKS[1:0] Frequency

Source

00b

PCLK divided by 4 (8.3 MHz. max)

The IC drives PICCLK.

01b

PCLK divided by 2 (16.7 MHz. max)

The IC drives PICCLK.

10b

PCLK (33.3 MHz. max)

The IC drives PICCLK.

11b

Unknown. Note: In this mode, the external

clock source is required to be 33.3 MHz or less.

PICCLK is driven by an external component.

C0A51: LPC Bus Decode Register 0

Configuration space; function 0; offset: 51h Default: 00h Read-write.

321:0

ACPI

KBDC

FDC2

FDC1

ECP

Reserved

PRANGE

PRANGE and ECP. Parallel port range and ECP enable. Specifies which parallel port IO range to route to the LPC

bus as follows:

PRANGE

ECP = 0

ECP = 1

00b

3BC - 3BFh

3BC - 3BFh and 7BC - 7BFh

01b

378 - 37Fh

378 - 37Fh and 778 - 77Fh

10b

278 - 27Fh*

278 - 27Fh and 678 - 67Fh*

11b

None

* Note: Port 279h is read-only for LPC. Writes are forwarded to the ISA bus.

FDC1. Floppy drive controller 1. 1=IO ports 3F0h - 3F5h and 3F7h is are routed to LPC. 0=These accesses are

routed to the ISA bus.

FDC2. Floppy drive controller 2. 1=IO ports 370h – 375h and 377h is are routed to LPC. 0=These accesses are

routed to the ISA bus.

KBDC. Keyboard controller. 1=When USB keyboard emulation is not enabled via HceControl[0] (offset 100h in

USBxxx space), IO ports 60h and 64h are routed to LPC. 0=When USB keyboard emulation is not enabled, IO ports

60h and 64h are routed to ISA. If USB keyboard emulation is enabled, these cycles are routed to the USB block.

ACPI. ACPI controller. 1= IO ports 62h and 66h are routed to LPC. 0=These accesses are routed to the ISA bus.

AMD-766 Datasheet(PDF) 38 Page - Advanced Micro Devices

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