BT261 datasheet(16/56 Pages) ETC

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Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Brooktree®

CIRCUIT DESCRIPTION

Phase/Frequency Detector Operation

L261_H

Phase/Frequency Detector Operation

The phase comparator compares the phase of the falling edge of the noise-gated

CSYNC* and generated HSYNC. The HSYNC can be either internally generated

(and optionally output onto the HSYNC pin) or an external HSYNC signal can be

input via the HSYNC pin.

Two Forms of Noise Gating Available

The Bt261 offers two forms of noise gating to remove half-line serration and

equalization pulses during the vertical interval, which can cause loop disturbances

and wavering at the beginning of the displayed ﬁeld. The ﬁrst is a digital noise gate

that is programmed in pixel clock events following the falling edge of composite

sync. The noise-gate start must occur before the halfway point (HCOUNT/2). The

noise-gate stop value must relate to a clock count a maximum distance from the

end of line, deﬁned as one half the minimum width of the serration pulse, less 500

ns. One half the equalization pulse provides the maximum error deviation for cor-

rect phase comparison. The 500 ns delay is required because of the offset used dur-

ing phase limiting. Even when phase limiting is disabled, this delay is included in

both the noise-gated CSYNC* and generated HSYNC* paths. Therefore, it must

be accounted for in the noise-gate stop value (see Figure 3 [a–d]). The earliest pos-

sible noise-gate stop value permits the widest phase-error tracking range. For an

acquisition range greater than one half the minimum equalization pulse width

(

±2.3 µs or 3.6 percent of nominal RS170A), the noise gate should be set transpar-

ent by programming a start value greater than HCOUNT and a stop value less than

HCOUNT until lock is veriﬁed in the active ﬁeld. The status registers can be mon-

itored to verify lock.

BT261 Datasheet(PDF) 16 Page - List of Unclassifed Manufacturers