BT261 datasheet(35/56 Pages) ETC

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Brooktree®

L261_H

INTERNAL REGISTERS

CLAMP Start and Stop Registers

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

CLAMP Start and Stop Registers

These two 16-bit registers specify the horizontal count (in pixel clocks) at which to assert and negate the CLAMP out-

put. The [start value] speciﬁes the number of CLOCK cycles after the falling edge of noise-gated CSYNC* that

CLAMP is set high. The [stop value] speciﬁes the number of CLOCK cycles after the falling edge of noise-gated

CSYNC* that CLAMP is set low. If [start value] = [stop value], CLAMP will remain a constant logical one. Values

from $0000 (1) to $0FFF (4096) may be speciﬁed. There is a 3-pixel-clock pipeline delay in clearing the horizontal

counter when the part is used in phase-lock loop mode. When the pixel clock is generated by dividing down an ex-

ternal oscillator, this delay is in oscillator clocks. Thus, output of this signal with respect to CSYNC* may be delayed.

D4–D7 of CLAMP start high are ignored during MPU write cycles and return a logical zero during MPU read cy-

cles. The 16-bit CLAMP start register is not updated until the write cycle to the CLAMP start high register. Thus, the

writing sequence should be [clamp start low] [clamp start high].

D4–D7 of CLAMP stop high are ignored during MPU write cycles and return a logical zero during MPU read cy-

cles. The 16-bit CLAMP stop register is not updated until the write cycle to the CLAMP stop high register. Thus, the

writing sequence should be [clamp stop low] [clamp stop high].

A value corresponding to 1

µs after the falling edge of CSYNC* is recommended for the [start] value, and a value

of 1

µs before the rising edge of CSYNC* is recommended for the [stop] value if DC restoration is to occur during

the horizontal sync interval. If DC restoration is to occur during the back porch interval, a value corresponding to 500

ns after the rising edge of CSYNC* is recommended for the [start] value and a value corresponding to 2.5

µs after the

rising edge of CSYNC* is recommended for the [stop] value. For restoration of signals with subcarrier-encoded

NTSC or PAL, the 7.8–9.4

µs interval (12–15 percent of HCOUNT) following the color burst may be better for

clamping a luminance signal with residual burst.

CLAMP Start/Stop High

CLAMP Start/Stop Low

Data Bit

Cascaded Value

H11

H19

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