BT261 datasheet(11/56 Pages) ETC

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CIRCUIT DESCRIPTION

Horizontal Counter

L261_H

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Horizontal Counter

The rising edge of pixel clock (CLOCK) increments a 12-bit horizontal counter

used to generate horizontal video timing information. The value of the counter is

compared to various registers to determine when signals are to be asserted (set

high) and negated (set low). $000 corresponds to the falling edge of CSYNC*.

When the part is used with an external high-speed oscillator and divided down to

generate the pixel clock, there is no pipeline delay between CSYNC* and count

zero. However, when the part is used in phase locked loop mode with an external

VCO, there is a three-pixel-clock pipeline delay between CSYNC* and count zero.

Horizontal Sync Separation

The Bt261 separates horizontal sync information from CSYNC* by use of the hor-

izontal noise gate register, which derives gated composite sync by removing equal-

ization and serration pulses at half-line intervals.

Two 12-bit noise gate start and stop registers specify at what horizontal count

(with pixel clock resolution) to respectively ignore or accept falling sync transi-

tions on CSYNC*.

The sync noise gating is provided to ﬁlter incorrect horizontal sync information

from noisy video signals. The noise gating also serves a second purpose: to ﬁlter

serration and equalization pulses at half-line intervals from CSYNC* during the

vertical retrace interval. This enables steady synchronization of horizontal sync in-

formation during vertical retrace intervals.

HSYNC Input/Output

The HSYNC output may be programmed to be either active high or active low.

The start value sets the rising edge and the stop value sets the falling edge of

HSYNC relative to count zero of the horizontal counter. The beginning or falling

edge of HSYNC is typically programmed to be coincident with the beginning of

the noise-gated CSYNC*.

The HSYNC output may be three-stated via the command register.

HSYNC may also be conﬁgured as an input, enabling external circuitry to generate

HSYNC and drive the phase comparator.

BT261 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers