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BT261 Datasheet(PDF) 12 Page - List of Unclassifed Manufacturers |
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BT261 Datasheet(HTML) 12 Page - List of Unclassifed Manufacturers |
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12 / 56 page ![]() Bt261 30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller Brooktree® 6 CIRCUIT DESCRIPTION VSYNC* Output L261_H VSYNC* Output The VSYNC register defines the clock count from the falling edge of nongated CSYNC* at which point CSYNC* is sampled to determine if the video signal is in the vertical interval. Since nongated CSYNC is used to start the VSYNC counter, two samples per horizontal line are taken during the vertical interval because of equalization and serration pulses. For each scan line that the sample is a logical zero, the VSYNC* output is a log- ical zero. Thus, the VSYNC sample register should be programmed so that the sample occurs well after the end of CSYNC* and before subsequent equaliza- tion/serration pulses. VSYNC is output on the rising edge of PCLK. FIELD Output The FIELD output is derived from the vertical sync information. By positioning the FIELD gate start/stop values a half-line interval apart, the half-line delay in vertical sync during the second field's vertical interval can provide a signal to dis- tinguish the fields. The FIELD output is clocked by VSYNC*. Therefore, FIELD start and stop values should not coincide with VSYNC or VSYNC + HCOUNT/2. The FIELD GATE start and stop values define the clock count, from the beginning of the hor- izontal counter, at which to set the input to a register high (start value) or low (stop value). This register is clocked by VSYNC, which occurs half a line later in the transition from field 1 to field 2. The FIELD start and stop values must be separated by, approximately, HCOUNT/2, so that opposite states are reported on subsequent fields. The polarity is such that, with the FIELD GATE start value programmed less than the stop value, FIELD output is toggled high to indicate the beginning of field 1 and toggled low to indicate the beginning of field 2. The polarity of the FIELD pin may be inverted by swapping the start and stop register values. Figure 1 illustrates the operation of the FIELD gate and FIELD output. |
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