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BT261 Datasheet(PDF) 41 Page - List of Unclassifed Manufacturers

Part # BT261
Description  30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
PDF  56 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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BT261 Datasheet(HTML) 41 Page - List of Unclassifed Manufacturers

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Brooktree®
35
L261_H
APPLICATION
INFORMATION
Phase Locking With the 74HC4046
Applications that call for multiple resolutions with clock rates in the 9–18 MHz
range may employ the circuit (Figure 10) shown with a 74HC4046 and a passive
loop filter. Residual jitter can be less than 30 ns, which is subpixel but not as good
as can be achieved with LC-tuned VCOs or VCXOs. These have narrower tuning
ranges. The loop parameters were obtained from a design program provided for the
74HC4046 with the Bt261’s phase comparator emulating the type 2 phase detector
with 4
π/VCC gain (Note 1). The type 1 second-order loop is designed for 10 dB
ripple suppression in closed-loop response with a critically damped response and
a tracking range of 4 percent, which is adequate for most stable sources (e.g.,
broadcast, camera, and videodisc). Nonstandard video sources (e.g., heterodyne
VCRs or floppy disk ESP cameras) may require a prefilter PLL for adequate track-
ing. Third-order loop filters may yield faster loop response rolloff, which reduces
jitter but can prolong loop settling time.
The same circuit can be extended to 26 MHz for genlocking to higher raster fre-
quency sources (such as noninterlaced VGA) or adapted to crystal-based operation
up to 10 MHz. The VCO timing-capacitor value must be reduced to 40 pF for the
former higher frequency case or replaced with a parallel resonant crystal in the lat-
ter case. Loop filter values will vary slightly in conjunction with modification of
R1 and R2 VCO gain-setting resistors.
In general, VCO capture range must be limited to one octave to prevent harmon-
ic lockup. With the low-input bias current of the 74HC4046, passive filters are sim-
pler than active filters and can better accommodate large-value polarized
capacitors. Bipolar VC(X)O implementations that use the MC4024, 74LS624, or
MN3106 require active buffers with bias currents less than 10
µA to limit control
voltage droop across the 64
µs interval between phase-comparison pulses.
Low-absorption Mylar or Teflon capacitors in the loop filter can minimize jitter
caused by capacitance modulation.



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