BT261 datasheet(29/56 Pages) ETC

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L261_H

INTERNAL REGISTERS

Command Register_2

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Command Register_2

This command register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to D0

and is the least signiﬁcant bit.

CR27, CR24

Phase lock pixel count

(0001) 2 clock cycles

(1111) 16 clock cycles

These bits specify the maximum number of pixel clock

cycles between the falling edge of noise-gated

CSYNC* and the HSYNC signal (either internally or

externally generated) to be considered locked.

If the number of pixel clock cycles between the falling

edge of noise-gated CSYNC* and the HSYNC signal

exceed this value, lock is considered to be lost for that

scan line, and the lock loss status bit (SR00) is set to

a logical zero.

CR23

Pixel clock mask enable

(0)

continuous pixel clock

(1)

stop pixel clock at HCOUNT

If this bit is a logical one, the CLOCK output is

stopped in the logical one state when the horizontal

counter reaches the HCOUNT value. This ensures a

minimum pulse width when the noise-gated CSYNC*

signal is asynchronously sampled. If it is a logical

zero, the CLOCK output will continuously clock (if

command bit CR16 is a logical zero).

This bit is

ignored if an external pixel clock is driving the CLOCK

pin (command bit CR16 is a logical one).

CR22

Lock override

(1)

normal operation

(0)

tell phase comparator it's locked

If the Bt261 goes out of lock, the phase limiter is auto-

matically disabled until it is back in lock. If this bit is a

logical zero, this function is overridden.

CR21, CR20

Pixel clock select

(00)

OSC inputs

(01)

external pixel clock

(10)

OSC drives CLOCK direct

(11)

reserved

These bits specify whether to use the OSC-generated

pixel clock or an external pixel clock (driving the

CLOCK pin) to clock internal counters.

In mode (00), the selected OSC input(s) is divided

down by the OSC count registers to generate the

pixel clock (CLOCK).

If mode (01) is selected, an external pixel clock must

drive the CLOCK pin and one of the OSC inputs.

Command bit CR16 must be a logical one.

If mode (10) is selected, the OSC clock is output

directly onto the CLOCK pin. The OSC count low and

high registers are ignored.

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