BT261 datasheet(31/56 Pages) ETC

31 / 56 page

Brooktree®

L261_H

INTERNAL REGISTERS

Status Register

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

Status Register

This status register may be read by the MPU at any time and is not initialized. MPU write cycles to this register are

ignored. SR00 corresponds to D0 and is the least signiﬁcant bit.

SR00

Lock-loss status (pixel count related)

(0)

lock loss detected

(1)

reset or no lock loss

This bit reset if loss of lock is indicated. “Loss of lock” is

deﬁned as a greater phase error between noise-gated

CSYNC* and generated HSYNC* than the phase-lock

pixel count (CR27–CR24). It is reset by writing to com-

mand bit CR12.

SR05

Lock-loss bit (line-count related)

(1)

lock loss detected

(0)

lock detected for at least

line-count number of lines

This bit is set if one line of video has a phase error

between generated HSYNC and noise-gated CSYNC*

greater than that deﬁned by the phase-lock pixel count

(CR24–CR27). This bit is reset if there have been

phase-lock line count (CR37–CR30) consecutive lines

with error less than that deﬁned in the phase-lock pixel

count.

BT261 Datasheet(PDF) 31 Page - List of Unclassifed Manufacturers