BT261 datasheet(27/56 Pages) ETC

27 / 56 page

Brooktree®

L261_H

INTERNAL

REGISTERS

Horizontal Counter

The 12-bit horizontal counter is incremented on the rising edge of CLOCK. It is not accessible by the MPU.

Command Register_0

This command register may be written to or read by the MPU at any time and is not initialized. CR00 corresponds

to D0 and is the least signiﬁcant bit.

CR07, CR06

Horizontal counter control

(00)

reserved

(01)

reset each noise-gated

CSYNC*

(10)

reset to zero upon reach-

ing HCOUNT

(11)

use both modes (01) and

(10)

A value of (01) forces the horizontal counter to be reset to zero

at the beginning of every noise-gated CSYNC*. These modes

should be selected when using a high–speed oscillator to

divide down and generate the pixel clock.

A value of (10) speciﬁes that the horizontal counter will be

reset to zero upon reaching the HCOUNT value. This mode

should be selected when using the horizontal counter as a sim-

ple divide-by-N circuit (such as when using an external VCO in

a traditional phase-locked loop application). Mode 11 can be

used to correct for missing sync pulses on the input video.

CR05

Capture strobe

This bit is synchronized to VSYNC* and FIELD and output onto

the CAPTURE output pin.

CR04, CR03

Sync detect select

(00)

25 mV

(01)

50 mV

(10)

100 mV

(11)

125 mV

These bits specify how much above the sync tip to slice VIDEO

for sync detection. If inputting TTL sync information, the high-

est slicing level should be selected.

CR02-CR00

Clock input select

(000) TTL compatible OSC1

(001) TTL compatible OSC1*

(010) TTL compatible OSC2

(011) TTL compatible OSC2*

(100) ECL compatible OSC1,

OSC1*

(101) ECL compatible OSC2,

OSC2*

(110) reserved

(111) reserved

These bits specify which OSC input is to be used to generate

pixel clock information. ECL input selection is compatible with

10KH differential ECL driven by a single +5 V supply.

Note:

When the clock pin is driven, the selected OSC pin(s)

must also be driven.

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