BT261 datasheet(28/56 Pages) ETC

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L261_H

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

INTERNAL REGISTERS

Command Register_1

This command register may be written to or read by the MPU at any time and is not initialized. CR10 corresponds

to D0 and is the least signiﬁcant bit.

CR17

Interlaced or noninterlaced select

(0)

noninterlaced operation

(1)

interlaced operation

This bit speciﬁes whether an interlaced or noninterlaced video

signal is being digitized. The MPU must write a logical zero fol-

lowed by a logical one to this bit to reset the status bit (SR00)

to a logical one.

CR16

CLOCK output disable

(0)

drive CLOCK output

(1)

three-state CLOCK out-

put

This bit speciﬁes whether the CLOCK pin is three-stated (logi-

cal one) or is actively driven (logical zero).

A logical one

enables an external pixel clock to drive the internal counters.

CR15

CSYNC* output disable

(0)

drive CSYNC* output

(1)

three-state CSYNC* out-

put

This bit speciﬁes whether the CSYNC* output is three-stated

(logical one) or is actively driven (logical zero).

CR14

VSYNC* output disable

(0)

drive VSYNC* output

(1)

three-state VSYNC* out-

put

This bit speciﬁes whether the VSYNC* output is three-stated

(logical one) or is actively driven (logical zero).

CR13

HSYNC output disable

(0)

drive HSYNC output

(1)

three-state HSYNC out-

put

This bit speciﬁes whether the HSYNC output is three-stated

(logical one) or is actively driven with the internally generated

HSYNC signal (logical zero). If external circuitry is driving the

HSYNC pin, this bit must be set to a logical one.

CR12

Reset lock loss status bit

(0)

set status bit SR00

(1)

inactive

This bit sets SR00, which is used to indicate loss of lock. The

MPU must write a logical zero to this bit to restart the process.

CR11

Phase comparator input select

(0)

HSYNC pin

(1)

internally generated

HSYNC

One input to the phase comparator is recovered composite

sync. The other input to the phase comparator is speciﬁed by

this bit to be either the internally generated HSYNC or the

HSYNC pin. When an external source is driving the HSYNC

pin, this bit should be set to a logical zero.

CR10

Phase limit enable

(0)

inhibit phase limiting

(1)

enable phase limiting

If this bit is a logical one, both horizontal sync signals (recov-

ered and either internally or externally generated) must be

present to adjust the VCO frequency. If one is missing, the

VCO frequency is not adjusted. If this bit is a logical zero, a

missing horizontal sync signal will adjust the VCO frequency.

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