BT261 datasheet(37/56 Pages) ETC

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Brooktree®

L261_H

INTERNAL REGISTERS

FIELD Gate Start and Stop Registers

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

FIELD Gate Start and Stop Registers

These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at

which to start and stop the FIELD gate "window." With the noise gate properly programmed to ignore half-line ver-

tical interval pulses, the VSYNC* transition will occur half a line later during the vertical sync interval between ﬁelds

one and two (assuming a typical 2:1 interlaced video signal). By programming the FIELD start and stop values to

have an interval exceeding half a line (e.g. starting at 1/4 line time and stopping at 3/4 line time), the FIELD output

is low during ﬁeld one if [start value] < [stop value] or high during ﬁeld one if [start value] > [stop value], with tran-

sitions at every falling edge of VSYNC*. If [start value] = [stop value], FIELD will remain a constant logical one.

Values from $0000 (1) to $0FFF (4096) may be speciﬁed. Field edge coincides with VSYNC* falling edge.

D4–D7 of FIELD gate start high are ignored during MPU write cycles and return a logical zero during MPU read

cycles. The 16-bit FIELD gate start register is not updated until the write cycle to the FIELD gate start high register.

Thus, the writing sequence should be [ﬁeld gate start low] [ﬁeld gate start high].

D4–D7 of FIELD gate stop high are ignored during MPU write cycles and return a logical zero during MPU read

cycles. The 16-bit FIELD gate stop register is not updated until the write cycle to the FIELD gate stop high register.

Thus, the writing sequence should be [ﬁeld gate stop low] [ﬁeld gate stop high].

Values of one fourth HCOUNT and three fourths HCOUNT are recommended for start and stop values, resulting

in an active high FIELD output (ﬁeld one = 1, ﬁeld two = 0).

FIELD Gate Start/Stop

High

FIELD Gate Start/Stop Low

Data Bit

Cascaded Value

H11

H19

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