BT261 datasheet(34/56 Pages) ETC

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Brooktree®

L261_H

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

INTERNAL REGISTERS

HSYNC Start and Stop Registers

These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at

which to assert or negate the HSYNC output. The [start value] speciﬁes the number of CLOCK cycles after the falling

edge of noise-gated CSYNC* that the HSYNC output is set high. The [stop value] speciﬁes the number of CLOCK

cycles after the falling edge of noise-gated CSYNC* that the HSYNC output is set low. If [start value] = [stop value],

HSYNC will remain a constant logical one. Values from $0000 (1) to $0FFF (4096) may be speciﬁed. Note that there

is a variable pipeline delay between the CSYNC* and HSYNC outputs. There is a 3-pixel-clock pipeline delay in

clearing the horizontal counter when the part is used in phase-lock loop mode. When the pixel clock is generated by

dividing down an external oscillator, this delay is in oscillator clocks. Thus, output of this signal with respect to

CSYNC* may be delayed.

D4–D7 of HSYNC start high are ignored during MPU write cycles and return a logical zero during MPU read cy-

cles. The 16-bit HSYNC start register is not updated until the write cycle to the HSYNC start high register. Thus, the

writing sequence should be [HSYNC start low] [HSYNC start high].

D4–D7 of HSYNC stop high are ignored during MPU write cycles and return a logical zero during MPU read cy-

cles. The 16-bit HSYNC stop register is not updated until the write cycle to the HSYNC stop high register. Thus, the

writing sequence should be [HSYNC stop low] [HSYNC stop high].

HSYNC Start/Stop High

HSYNC Start/Stop Low

Data Bit

Cascaded Value

H11

H19

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