BT261 datasheet(9/56 Pages) ETC

9 / 56 page

Brooktree®

L261_H

CIRCUIT

DESCRIPTION

MPU Interface

As seen in the functional block diagram, the Bt261 supports an MPU interface via

(D0–D7, RD*, WR*, and A0). MPU operations are asynchronous to the clocks.

Refer to the Timing Waveforms section for further information.

A0 is used to select either the internal 5-bit address register (A0 = logical zero)

or the control register speciﬁed by the address register (A0 = logical one).

ADDR5–ADDR7 are ignored during MPU write cycles, and are in an unknown

state when read by the MPU. ADDR0 corresponds to D0 and is the least signiﬁcant

bit. ADDR0–ADDR4 increment following any MPU read or write cycle to a con-

trol register other than the address register. MPU write cycles to reserved address-

es are ignored and MPU read cycles from reserved addresses return invalid data.

Table 1 shows the internal register addressing.

Table 1. Internal Register Addressing

ADDRO - ADDR4

Addressed by MPU

$00

command register_0

$01

command register_1

$02

command register_2

$03

command register_3

$04

VSYNC sample register

$05

OSC count low register

$06

OSC count high register

$07

status register

$08

HSYNC start low register

$09

HSYNC start high register

$0A

HSYNC stop low register

$0B

HSYNC stop high register

$0C

CLAMP start low register

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