BT261 datasheet(17/56 Pages) ETC

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CIRCUIT DESCRIPTION

Two Forms of Noise Gating Available

L261_H

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

A second analog noise gate is activated through the phase-limit feature. This

function limits the duration of phase correction to about 500 ns per coincidence of

noise-gated CSYNC* and generated HSYNC. The Phase Frequency Detector

(PFD) makes its comparison about 500 ns after each falling transition of either

HSYNC or CSYNC*. However, with phase limiting enabled, the comparison oc-

curs only for a 500 ns interval while both signals are low. Thus, by limiting phase

comparison to a 500 ns window, transitions at half-line intervals are not detected.

The phase truncation that occurs when this feature is used limits the instantaneous

phase-error impulse to about 500 ns that the loop can track. This may not be ade-

quate for some video signal sources, such as heterodyne VCRs (without time-base

correction) or electronic still photography (e.g., ﬂoppy disk) cameras. If the Bt261

is programmed to permanently phase limit (CR22 set low), the phase-comparison

duty is only ~0.8 percent and loop settling time is prolonged dramatically.

Figure 3, Figure 4, and Figure 5 are block diagrams and examples demonstrating

noise gating and phase limiting.

Both forms of noise gate can be used together for maximum acquisition range

with phase-error impulse tracking up to ~3.6 percent of the line rate (the maximum

depends upon the minimum width of serration pulses). For an acquisition range

that exceeds

±2.3 µs, the digital noise gate must be set transparent by temporarily

setting noise-gate start value greater than HCOUNT with a stop value less than

HCOUNT. Acquisition can then be automatic and the phase-limit feature (CR10 =

CR22 = 1) can be used with phase-lock pixel count (CR27–CR24) programmed

for less than 500 ns and the phase-lock line count (CR37–CR30) programmed for

less than the ﬁeld line count, minus the closed-loop settling time. When phase lock

is veriﬁed (by strobing CR10 low and reading back SR0 = 1 or monitoring SR05),

the digital noise-gate can be reactivated by restoring the noise-gate start value to

less than HCOUNT/2. When the digital noise gate is active, the phase-limit feature

should be disabled for maximum phase-error tracking range (determined by the

phase-lock loop’s closed-loop impulse response, but limited by one-half minimum

serration pulse or noise-gate width). If instantaneous phase errors exceed

phase-lock pixel count, the status register SR00 bit is forced to zero, even though

the loop may be tracking the phase-error impulses. Since large phase errors usually

occur in the vertical blanking interval, it is prudent to reset and monitor the lock

status bit after the phase-lock line count has expired in the active ﬁeld. A consistent

zero in SR00 would dictate restarting the acquisition sequence outlined above to

maintain phase lock. Similarly, SR05 may be monitored to determine locking sta-

tus.

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